A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Brandon, T.L.; Hang, Robert; Block, Gary; Gaudet, Vincent; Cockburn, B.F.; Howard, S.L.; Giasson, Christian; Boyle, Keith; Goud, P.A.; Zeinoddin, Siavash Sheikh; Rapley, Anthony; Bates, Stephen; Elliott, D.G.; Schlegel, Christian

doi:10.1016/j.vlsi.2007.07.003

Cited by 28 publications

(13 citation statements)

References 25 publications

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“…An (n, k) LT code is typically decoded according to a bipartite graph known as a factor graph which corresponds to the parity check matrix H of the code [8]. This kind of factor graph contains two nodes: variable nodes and parity check nodes.…”

Section: Lt Decoding Architecturesmentioning

confidence: 99%

Design and implementation of LT codec architecture with optimized degree distribution

Alam

Choi

2013

IEICE Electron. Express

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Abstract:In this paper, we present an architecture for ASIC realizations of the Luby Transform (LT) encoder and decoder. To determine the efficiency of the LT Codec architecture, the encoder and decoder are implemented with a core area of 9 mm 2 in TSMC 180-nm 1-poly 6-metal and Samsung 130-nm complementary metal-oxidesemiconductor (CMOS) technology. An empirically modified Robust Soliton degree distribution technique is applied for LT Codec implementation and its performance is analyzed in terms of chip area and cycle count. Instead of including a random generator in the register transfer level (RTL) design, we use different look-up tables (LUTs) for degree distribution, edge routing, addressing and inverse edge routing. Therefore, this architecture is efficient for hardware implementation and occupies less area inside the chip. The result shows that an area of 2.3 mm 2 is required for whole encoder and decoder implementation using TSMC library, of which 0.08 mm 2 is used for encoder implementation. Finally, a modified Robust Soliton degree distribution technique is presented and evaluated in terms of cycle count for different number of iterations using Tensilica tool. Result shows that it takes very less iterations which is more beneficial for hardware implementation of LT Codec.

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Section: Lt Decoding Architecturesmentioning

confidence: 99%

Design and implementation of LT codec architecture with optimized degree distribution

Alam

Choi

2013

IEICE Electron. Express

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“…To apply these node-processing units, an efficient router and reverse router are designed to indicate the graphic connectivity between input and output nodes. Brandon et al presented a scalable bit serial architecture for a low-density parity check (LDPC) decoder [4]. In here, the decoder was implemented for a (256,128) regular ð3; 6Þ LDPC code using Taiwan semiconductor manufacturing company (TSMC) 180 nm 6-metal CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

“…In here, the decoder was implemented for a (256,128) regular ð3; 6Þ LDPC code using Taiwan semiconductor manufacturing company (TSMC) 180 nm 6-metal CMOS technology. It has decoded information throughput of 350 Mbps, a core area of 6.96 mm 2 , and energy efficiency at 7.56 nJ per un-coded bit at low signal to noise ratio (SNR) [4]. There are some other unpublished works based on the FPGA implementation of an LT codec application [5].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a novel LT codec architecture on TTA based codesign environment

Alam

Choi

2016

IEICE Electron. Express

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Abstract:The main aim of this paper is to explain the generation technique of application specific function units (FUs) for reducing the number of instructions in Luby Transform (LT) codec processor. For this reason, Transport Triggered Architecture (TTA) is taken as an active processor template for designing a high-speed TTA-based LT codec processor using TTA-based Co-design Environment (TCE) tool. In this design, processor architectures named as P 1 , P 2 , P 3 , P 4 , P 5 , and P 6 are generated to gradually improve the performance of the TTA processor. P 6 took only 4,466 cycles and 43 ms to simulate an LT codec system. In this paper, P 6 of the TCE tool took only a single iteration to generate the decoded signal.

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“…Another approach used to alleviate the routing congestion problem is to use bit-serial or digit-serial architectures to implement LDPC decoders. Examples of this approach are the recent FPGA implementation of a bit-serial (480,355) LDPC decoder in [21], the ASIC implementation of a (660,480) LDPC decoder in [12] based on bit-serial approximate MSA, and the MSA-based bit-serial (256,128) LDPC decoder in [22]. Also, a message broadcasting technique was recently suggested to alleviate the routing congestion by reducing node-to-node communication complexity in LDPC decoders [13].…”

Section: Introductionmentioning

confidence: 99%

Fully Parallel Stochastic LDPC Decoders

Tehrani

Mannor

Gross

2008

IEEE Trans. Signal Process.

183

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Abstract-Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) decoders. To obtain the characteristics of the proposed architecture, we apply this architecture to decode an irregular state-of-the-art (1056,528) LDPC code on a Xilinx Virtex-4 LX200 field-programmable gate-array ( Index Terms-Field programmable gate arrays (FPGAs), iterative decoding, low-density parity-check (LDPC) codes , stochastic decoding.

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A scalable LDPC decoder ASIC architecture with bit-serial message exchange

Cited by 28 publications

References 25 publications

Design and implementation of LT codec architecture with optimized degree distribution

Design and implementation of LT codec architecture with optimized degree distribution

Design and implementation of a novel LT codec architecture on TTA based codesign environment

Fully Parallel Stochastic LDPC Decoders

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