A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities

Liu, Muqing; Everson, Luke; Kim, Chris H.

doi:10.1109/cicc.2017.7993627

Cited by 33 publications

(18 citation statements)

References 3 publications

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“…In addition, REC is more flexible when it comes to the extension of the input bits since the PE is designed once, and then used every clock cycle; however, for SU the PE needs to be repeated for every input, limiting its scalability. Finally, the SU and REC accelerators are implemented as all-digital, and their performance can be improved if custom-designed analog delay cells, DTC, and TDC are used similar to the work in [6], [7], [9]- [11].…”

Section: Results and Analysismentioning

confidence: 99%

“…TD cores can be implemented using two different architectures, including spatially unrolled (SU) [6], [7], [9] and recursive (REC) [10], [11]. In the SU architecture, inputs and weights are stored in spatially distributed storage elements with a dedicated processing element (PE).…”

Section: Introductionmentioning

confidence: 99%

“…The main contributions of this paper can be summarized as follows. First, unlike the work proposed in [6], [7], [9], [11], where analog design flow is used or custom analog blocks are needed, such as DTC and TDC, we implement TD cores for both SU and REC architectures using the digital flow synthesized in a 65nm CMOS technology. We also implement an identical digital core using the same technology for comparative purposes.…”

Section: Introductionmentioning

confidence: 99%

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A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks

Maharmeh

Sarhan

Hung

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a comprehensive analysis of hardware accelerators for neural networks in both the digital and time domains, where the latter includes spatially unrolled (SU) and recursive (REC) architectures. All accelerators are implemented and synthesized in a 65nm CMOS technology. An identical neural network model is implemented in the digital and time domain for comparative purposes in terms of throughput, power consumption, area, and energy efficiency. Post-synthesis results show that SU achieves the highest energy efficiency of 145 T Op/s/W with a throughput of 4 GOp/s. The digital core is the fastest among other cores, whereas REC is the slowest but is the most area-efficient, occupying 0.114 mm 2 . SU is more suited for applications with stringent power constraints and average performance, while REC is better suited for applications where the area is the most important requirement and the throughput is less significant. In contrast, the digital core is preferable for large neural networks and critical applications that require high performance.

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Section: Results and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks

Maharmeh

Sarhan

Hung

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Base on the digital-to-delay mechanism, TD cells can be classified into three categories: variable-capacitance (VC) cells, current-starve (CS) cells and tap-based (TB) cell as shown in Fig. 2 A time-based integrate-and-fire (IAF) neuromorphic core is present in [2]. The neuromorphic core is consisting of 64 digitally controlled oscillator (DCO) circuits, and each DCO has 128 VC cells.…”

Section: Td-sram Macro Analysis and Design A Td Cell Analysismentioning

confidence: 99%

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

Song

Wang

Guo

et al. 2021

IEEE Trans. Circuits Syst. I

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In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing. A dual-edge single input (DESI) TD computing topology is proposed, which can significantly improve the area and power efficiencies of TD cell. The TD-SRAM bitcell consisting of a 6T DESI based TD cell and a 6T-SRAM cell supports binary DNNs. In the IMC mode, 60 columns work in parallel and 96-input binary-MAC operations are processed in each column. Implemented in a standard 40-nm CMOS process, the TD-SRAM achieves the high energy efficiency of 537 TOPS/W at 0.9-V supply. With different DNN topologies, the test chips achieve the accuracy of 95.90%-98.00% with a dual 2-bit time-to-digital converter (TDC) in the MNIST dataset.

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“…We have already proposed a device and circuit that perform time-domain weighted-sum calculation [29]- [31]. Some AI processors based on different time-domain approaches have been reported recently [32]- [35]. Unlike these other approaches, our proposed circuit consists of plural input resistive elements and a capacitor (RC circuit), where the weights of the network are expressed by the resistance values.…”

mentioning

confidence: 99%

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

et al. 2021

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A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities

Cited by 33 publications

References 3 publications

A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks

A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

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