A Segmented SAR/SS ADC with Digital Error Correction and Programmable Resolution for Column-Parallel Sensor Arrays

Dai, Shanshan; Hu, Kangping; Rosenstein, Jacob K.

doi:10.1109/iscas45731.2020.9180940

Cited by 10 publications

(12 citation statements)

References 22 publications

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“…Additionally, a global ramp generator is shared by all columns. While the binary weighted successive approximation register (SAR) is energy efficient, it is susceptible to errors caused by digital-to-analog converter (DAC) settling and mismatches in DAC capacitors [23]. In contrast, a thermometer code offers several advantages over a binary code, including natural monotonicity, no missing codes, and superior DNL performance.…”

Section: Block Diagrammentioning

confidence: 99%

“…By ensuring monotonic features and avoiding glitches caused by voltage peaks, the segmented thermometer-coded DAC can reduce DNL while maintaining the same capacitor area [24]. For instance, an M-bit thermometer-coded While the binary weighted successive approximation register (SAR) is energy efficient, it is susceptible to errors caused by digital-to-analog converter (DAC) settling and mismatches in DAC capacitors [23]. In contrast, a thermometer code offers several advantages over a binary code, including natural monotonicity, no missing codes, and superior DNL performance.…”

Section: Block Diagrammentioning

confidence: 99%

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A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

Hu,

Yao,

Chen

et al. 2024

Sensors

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This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

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Section: Block Diagrammentioning

confidence: 99%

Section: Block Diagrammentioning

confidence: 99%

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

Hu,

Yao,

Chen

et al. 2024

Sensors

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“…In recent years, the research on ADC applied to the CIS field involved a large number of different ADC topologies, such as successive approximation ADC (SAR ADC) [ 1 ], σ-δ ADC [ 2 ], cyclic ADC (Cyclic ADC) [ 3 ], flash ADC (Flash ADC), pipeline ADC (Pipeline ADC) [ 4 ], single-slope ADC (SS-ADC) [ 5 ], and various combinations of the aforementioned ADC architectures. Considering the trade-off between speed, power consumption, and area, not every ADC structure is suitable for CIS [ 6 , 7 , 8 , 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

“…Its conversion time reached 625 ns, and the use of high-speed and high-gain operational amplifiers caused its power consumption to reach 435 μW. On a scale of 100 million, only the power consumption of this ADC structure would be close to 10 W, which limits its application in the CIS of a billion-level area array [ 7 , 8 , 9 , 10 , 11 , 12 ]. In view of the current research progress and existing problems, based on the traditional SS ADC, this paper proposed a high-speed fully differential two-step ADC structure applied to CIS, which can ensure the power consumption and area advantages of the SS ADC [ 13 , 14 ].…”

Section: Introductionmentioning

confidence: 99%

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Guo

Wang

2023

Sensors

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The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

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“…In this work, segmentation in the capacitors array was used as one solution to the chip area issue [6,16]. Nevertheless, a segmented architecture increases sensitivity to the capacitors' mismatch; thus, an additional digital calibration algorithm is necessary [16][17][18][19][20][21][22]. Many digital calibration architectures are very efficient; however, they increase both the circuit complexity and the total area.…”

Section: Introductionmentioning

confidence: 99%

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

Bontems

Dzahini

2023

Chips

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This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

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A Segmented SAR/SS ADC with Digital Error Correction and Programmable Resolution for Column-Parallel Sensor Arrays

Cited by 10 publications

References 22 publications

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

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