A self-biased PLL with low power and compact area

Abstract

A new low power, low phase jitter, compact realization, and self-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents. Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively. By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved. The PLL consumes 4.2 mW of power under 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mm 2 (180 110 m 2 /, and the typical period jitter (RMS) is around 2.8 ps.

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

“…Equations ( 18) and (19) show that the damping ζ and the loop bandwidth ω n to operating frequency ratio are constant, and are determined by the capacitance ratio. Equation (19) shows that, with a given N, the bandwidth is proportional to the input reference clock. When N is increased, the bandwidth increases to suppress more VCO noise to achieve better jitter performance.…”

“…However, the nonlinear capture behavior of a self-biased PLL results in very long power-up latency, which is unacceptable for most applications. With the bias generator, both the VCO delay cells currents and the charge-pump discharge/charge (I CP ) currents change with V CTRL by quadratic functions [18,19]. Therefore, a start-up circuit is needed to speed up PLL locking.…”