A self-calibration technique for monolithic high-resolution D/A converters

Groeneveld, D.W.J.; Schouwenaars, H.J.; Termeer, H.A.H.; Bastiaansen, Corné

doi:10.1109/4.44987

Cited by 189 publications

(8 citation statements)

References 6 publications

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“…Several other on-chip DAC calibration methods that do not increase the ELD, have been developed. Current-copying DAC calibration is presented by [19] and is widely adopted [3], [8]. Frequent refresh is performed to charge the capacitors, which store the calibrated voltage.…”

Section: B Dac Calibration Schemementioning

confidence: 99%

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Liu

Xing

Gielen

2021

IEEE J. Solid-State Circuits

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This article presents a continuous-time (CT) analog-to-digital converter for wireless communication systems with a high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in the signal transfer function (STF) to achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration is implemented to calibrate the mismatch of the outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces the quantization noise and the excess loop delay, achieving a CT-DT hybrid sixth-order NS without suffering from neither the problem of the CT-DT transfer function matching in a CT multistage NS topology nor the stability issue in a singleloop fully CT sixth-order topology. The prototype is fabricated in 28-nm bulk CMOS and is clocked at 1.7 GHz. With a bandwidth of 85 MHz, the analog-to-digital converter achieves 0-dB peaking STF, 74.4-dB signal to noise and SNDR and 87.5-dB spuriousfree dynamic range, while consuming 61.8-mW power, resulting in an excellent Schreier Figure-of-Merit (FoM S ) of 165.8 dB. Index Terms-2 b/cycle asynchronous successiveapproximation-register (ASAR), continuous-time (CT) analog-to-digital converter (ADC), flat signal transfer function (STF), noise-shaping (NS) QTZ, on-chip digital-to-analog converter (DAC) calibration, out-of-band blocker (OBB). I. INTRODUCTIONT HE ever more crowded radio spectrum causes great challenges to the design of wireless communication systems, in terms of increasing signal bandwidth (BW) as well as spectral performance. This makes continuous-time (CT) analog-to-digital converters (ADCs) more attractive for use in wireless applications due to their high dynamic range (DR), good power efficiency and implicit anti-aliasing property [1]-[3]. Fig. 1 shows the received spectrum at the antenna of the long-term-evolution advanced (LTE-A) standard [2], [4], [5]. For an inter-band contiguous carrier Manuscript

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Section: B Dac Calibration Schemementioning

confidence: 99%

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Liu

Xing

Gielen

2021

IEEE J. Solid-State Circuits

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“…In order to reduce distortion, the objective of physical level calibration is to make (11) constant, by physical means. The calibration can take the form of adjusting component values directly using laser trimming 59 , matching current sources to a common reference 17,20,21 , or adding or subtracting correction voltages at the output via a secondary DAC 18,60 . The latter method can be retrofitted to an existing system.…”

Section: A Physical Level Calibrationmentioning

confidence: 99%

“…The most accurate levels can be obtained using superconducting Josephson junctions 10,11 . Using more conventional semiconductors, more accurate levels can be produced using careful component selection 16 or using physical calibration [17][18][19][20][21] . Better accuracy can also be obtained using averaging techniques, such as dynamic element matching 12,[22][23][24][25] , large periodic high-frequency dithering 26 , and large high-pass noise dithering 27,28 .…”

Section: Introductionmentioning

confidence: 99%

Existing methods for improving the accuracy of digital-to-analog converters

Eielsen

Fleming

2017

Review of Scientific Instruments

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The performance of digital-to-analog converters is principally limited by errors in the output voltage levels. Such errors are known as element mismatch and are quantified by the integral non-linearity. Element mismatch limits the achievable accuracy and resolution in high-precision applications as it causes gain and offset errors, as well as harmonic distortion. In this article, five existing methods for mitigating the effects of element mismatch are compared: physical level calibration, dynamic element matching, noise-shaping with digital calibration, large periodic high-frequency dithering, and large stochastic high-pass dithering. These methods are suitable for improving accuracy when using digital-to-analog converters that use multiple discrete output levels to reconstruct time-varying signals. The methods improve linearity and therefore reduce harmonic distortion and can be retrofitted to existing systems with minor hardware variations. The performance of each method is compared theoretically and confirmed by simulations and experiments. Experimental results demonstrate that three of the five methods provide significant improvements in the resolution and accuracy when applied to a general-purpose digital-to-analog converter. As such, these methods can directly improve performance in a wide range of applications including nanopositioning, metrology, and optics.

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“…This basic idea was first proposed in [47], where the calibration of each cell was based upon the charge storage on the gate-source capacitance of CMOS transistors to create multiple copies of a reference current, and implemented in a 16-bit DAC.…”

Section: Digital Compensationmentioning

confidence: 99%

Continuous compensation of binary-weighted DAC nonlinearities in bandpass delta-sigma modulators

Gagnon¹

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A self-calibration technique for monolithic high-resolution D/A converters

Cited by 189 publications

References 6 publications

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Existing methods for improving the accuracy of digital-to-analog converters

Continuous compensation of binary-weighted DAC nonlinearities in bandpass delta-sigma modulators

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