A self-trimming 14-b 100-MS/s CMOS DAC

Bugeja, A.R.; Song, Bang‐Sup

doi:10.1109/4.890297

Cited by 130 publications

(82 citation statements)

References 19 publications

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“…A 14-bit static linearity has been achieved by using trimming, selfcalibration [230], and even intrinsically [231]. A typical problem in these DACs is the rapid increase in harmonic distortion when the signal frequency is increased.…”

Section: Introduction To Current Steering Dacsmentioning

confidence: 99%

“…The return-to-zero technique utilized in [233] yields a clear improvement in highfrequency SFDR compared to earlier reported DACs, but still has some limitations, such as the difficulty of providing large amplitudes to a low-resistance load, the complicated circuitry needed to handle signal dependent parasitics, and sensitivity to clock jitter, which is not relaxed, unlike in conventional DACs, when signal frequency is decreased. To alleviate the first two of these problems the same authors have proposed the track/attenuate technique [230], which is basically a switch put in parallel with the load to short the output during the DAC switching.…”

Section: Introduction To Current Steering Dacsmentioning

confidence: 99%

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Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Introduction To Current Steering Dacsmentioning

confidence: 99%

Section: Introduction To Current Steering Dacsmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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“…A current-steering DAC architecture, in which an analog part is composed of current sources, is almost exclusively used when appli-cations require high speed and high resolution such as mobile cellular networks [1]. A current-steering DAC has static problems.…”

Section: Introductionmentioning

confidence: 99%

A novel high-precision DAC utilizing tribonacci series

Hokazono

Kanemoto

Kanaya

et al. 2012

IEICE Electron. Express

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Abstract:A novel Digital-to-Analog Converter (DAC) utilizing Tribonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The proposed DAC has the features that the DNL can be superior to that of a binary DAC and the INL can be superior to that of a unary DAC. In the proposed DAC on a 0.18 μm CMOS process, the number of logic gates can be achieved an around 52% reduction compared to that of the unary DAC.

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“…During the remainder of a sampling period, the effect of these dynamic errors can be sufficiently small. Consequently, the linearity of a CS DAC can be improved if we make sure the DAC is not connected to the output during the time that the dynamic errors are significant; this is for example done in [30,36] in the form of an RZ output signal. However as mentioned in section 2.2, RZ results in much larger transients and increases demands on analog post-filtering while at the same time the delivered output power is decreased.…”

Section: The Interleaved Structurementioning

confidence: 99%

“…This is generally done by adding extra switching for the zero part in the output [30,36], although in recent years an alternative has been proposed: DRRZ (Digital Random Return-to-Zero) [37,38,39] or DMRZ/DEMDRZ (Dynamic-element-Matching and Digital Return-to-Zero) [22]. Both of these are essentially the same: the zero-phase of the output is not implemented by using separate switches, but instead by switching half of the current sources to the positive output, and the other half to the negative output.…”

Section: Extra Cascodes With Bleeding Current Sourcesmentioning

confidence: 99%

Time-interleaved high speed D/A converters

Olieman¹

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A self-trimming 14-b 100-MS/s CMOS DAC

Cited by 130 publications

References 19 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

A novel high-precision DAC utilizing tribonacci series

Time-interleaved high speed D/A converters

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