A Shift Register based Clause Evaluator for Reconfigurable SAT Solver

Safar, Mona; Shalan, Mohamed; El-Kharashi, M. Watheq; Salem, Ashraf

doi:10.1109/date.2007.364583

Cited by 11 publications

(5 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The approaches described in Safar et al [2006Safar et al [ , 2007, like our approach, are single FPGA approaches. However, in these approaches, the memory module storing the instance has to be reconfigured for different problem instances (or independent subinstances for large instances).…”

Section: Previous Workmentioning

confidence: 99%

FPGA-based hardware acceleration for Boolean satisfiability

Gulati

Paul

Khatri

et al. 2009

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. The experimental results and their analysis, along with the performance models are discussed. We show that an order of magnitude improvement in runtime can be obtained over MiniSAT (the best-in-class software based approach) by using a Virtex-4 (XC4VFX140) FPGA device. The resulting system can handle instances with as many as 10K variables and 280K clauses.

show abstract

Section: Previous Workmentioning

confidence: 99%

FPGA-based hardware acceleration for Boolean satisfiability

Gulati

Paul

Khatri

et al. 2009

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…The simplicity of our architecture enables achieving high clock rates with few hardware resources utilization as shown in [12,13].…”

Section: Proposed Sat Solvermentioning

confidence: 99%

“…Each register is first initialized to the value "0001000". It is either right shifted, left shifted, or standstill according to whether current assigned variable's value satisfies, unsatisfies, or does not affect the clause, respectively [12]. The Conflict Analyzer consists of an accumulator where a high bit indicates that the corresponding variable is a candidate backtrack variable.…”

Section: Proposed Sat Solvermentioning

confidence: 99%

A reconfigurable SAT-based automatic test pattern generator

Safar

Shalan

El-Kharashi³

et al. 2011

2011 IEEE GCC Conference and Exhibition (GCC)

Self Cite

View full text Add to dashboard Cite

With the increasing complexity of integrated circuits and transition to Systems-on-Chip (SoC) paradigm, Automatic Test pattern Generation (ATPG) becomes a crucial tool in the Electronic Design Automation (EDA) domain. ATPG based on Boolean Satisfiability (SAT) has been proposed as an alternative to classical structural algorithms for generating test patterns for single stuck-at faults in combinational circuits. SAT-based ATPG provides excellent balance of simplicity and robustness versus structural algorithms. However, a highly efficient and fast SAT solver in needed to overcome the time overhead incurred in extracting the SAT formula. In this paper, we propose a reconfigurable hardware SAT-based test pattern generator. For different circuits, compilation, synthesis and place-and-route overhead is eliminated. We demonstrate the feasibility of our approach by experimenting with ISCAS'85.Our proposed reconfigurable SAT-based test pattern generator achieves 20 times average speedup compared to software SATbased ATPG.

show abstract

“…It is either right shifted, left shifted, or standstill according to whether current assigned variable's value satisfies, unsatisfies, or does not affect the clause, respectively. A clause is unsatisfied when the leftmost bit of its corresponding shift register is '1' [11].…”

Section: Clause Evaluator (Ce)mentioning

confidence: 99%

“…This is achieved in milliseconds, eliminating compilation, synthesis, and placeand-route overhead. Pipelining allows retaining same clock frequency of an equivalent non-pipelined implementation [11], while enhancing performance by about three times. This paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Five-Stage Pipelined SAT Solver

Safar

El-Kharashi

Shalan

et al. 2009

2009 10th International Workshop on Microprocessor Test and Verification

Self Cite

View full text Add to dashboard Cite

Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a fivestage pipelined SAT solver. The first stage is a variable decider that, in the normal flow, assigns a free variable from a set of statically pre-ordered variables. In case of conflict, where one or more of the SAT CNF clauses is unsatisfied, the highest ordered variable from a pool of conflicting variables is reassigned or freed. The second stage fetches the effect of the current assigned variable on the SAT instance clauses from a memory pre-initialized with the effect of each variable on all clauses. This data is fed to the next stage, the clause evaluator. The fourth stage is the conflict detector that detects if there is a conflict and, if there is, it detects the index of the first unsatisfied clause. The last stage fetches the conflicting variables (variables in the unsatisfied clause) from a memory containing variables associated with each clause. Our approach's feasibility is evaluated through instances from the DIMACS benchmarks suite. Pipelining allows retaining same clock frequency of an equivalent non-pipelined implementation while achieving an average of three times speedup in performance.

show abstract

A Shift Register based Clause Evaluator for Reconfigurable SAT Solver

Abstract: Abstract

Cited by 11 publications

References 15 publications

FPGA-based hardware acceleration for Boolean satisfiability

FPGA-based hardware acceleration for Boolean satisfiability

A reconfigurable SAT-based automatic test pattern generator

A Reconfigurable Five-Stage Pipelined SAT Solver

Contact Info

Product

Resources

About