A SiC JFET driver for a 5 kW, 150 kHz three-phase PWM converter

Abstract

Silicon carbide (SiC) power semiconductor devices are capable of being operated at higher voltages, frequencies and temperatures than silicon power devices. These SiC device capabilities will provide the power electronics designer with new possibilities to produce compact designs. Presently the JFET is the only controlled turn off/on SiC device that is close to commercialization and available as restricted samples. However the JFET is a normally-on device that requires a negative gate voltage to turn off. In order to correctly design a gate driver one must understand the characteristics of the JFET. This paper presents a description of the JFET semiconductor structure, and the SiC JFET's static and dynamic characteristics from room temperature to 200°C. A SiC JFET gate driver circuit is presented and its performance described. The proposed gate driver improves the switching performance of the JFET by operating the gate in avalanche during the off time.

Comparison of a state of the art Si IGBT and next generation fast switching devices in a 4 kW boost converter

“…The gate driver circuit for the SiC JFET requires more attention since the device differs internally from IGBTs or MOSFETs [27]. Since the JFET is a depletion mode device, it is turned on with a control voltage of 0 V and a negative voltage must be applied to turn the device off.…”

“…Furthermore, at around −23 V, the gate-source junction enters reverse breakdown and hence a gate-source voltage of −20 V is usually recommended in order to fully turn the device off. In [27], a driver circuit for a normally-on JFET is proposed to overcome this particular issue with the reverse breakdown, and it is therefore used in this work. Where the detailed explanation of the gate driver can be found in [27], it is only mentioned here that three additional electronic components are needed and the reference voltage, once again, must be shifted.…”

“…In [27], a driver circuit for a normally-on JFET is proposed to overcome this particular issue with the reverse breakdown, and it is therefore used in this work. Where the detailed explanation of the gate driver can be found in [27], it is only mentioned here that three additional electronic components are needed and the reference voltage, once again, must be shifted. The two modifications for the SiC JFET gate driver are therefore: 1) Place a RCD network between the gate resistance and the gate of the JFET 2) Reference the source of the JFET to the positive supply voltage of the DC/DC converter output, i.e.…”

Experimental comparison of different gate-driver configurations for parallel-connection of normally-on SiC JFETs

“…In this paper three different gate-driver configurations are considered. They are all based on a gatedrive unit which has been previously proposed [13] and it is depicted in Fig. 4.…”

High-power modular multilevel converters with SiC JFETs

“…This voltage should be lower than the device pinch-off voltage, in order to keep the JFET turned-off. The gatedrive design is a standard one for the SiC JFETs and has been derived from [34]. The driver is supplied from 24 V integrated dc/dc converter and the gate-source voltage when the JFET is blocking equals to the pinch-off voltage, while it is equal to 0 V when it is conducting.…”