A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL

Li, Hongxing; Maddox, Mark; Coin, Michael C. W.; Buckley, William F.; Hummerston, Derek; Naeem, Naveed

doi:10.1109/isscc.2018.8310274

Cited by 41 publications

(24 citation statements)

References 2 publications

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“…Therefore, BIT(1)∼BIT(6) meet the requirements of Equation (3). For BIT(1)∼BIT (10), it can also be easily obtained that BIT(1)∼BIT(10) meet the requirements of Equation (3).…”

Section: Overall Functionmentioning

confidence: 94%

“…At present, the IC foundries can ensure capacitor units with a natural matching accuracy of about 10 bits. Therefore, if all the capacitors in BIT(1)∼BIT (10) are composed of unit capacitors, there is no need to introduce any calibrations for the lower 10-bit capacitor array. As can be seen from Fig.…”

Section: Overall Functionmentioning

confidence: 99%

“…Then we set the size of all unit capacitors and bridge capacitor B1 to 20µm × 19.4µm (the deviation is 0.6µm), and the sizes of the bridge capacitor B2 remain unchanged. The DNL values of BIT(6), BIT (10), BIT (11) and BIT (16) are shown in Table 4. It can be seen from Table 4 that in the optimized 5+5+6 bits segmented capacitor array, if there is a deviation in the size of the unit capacitor, the DNL values of BIT(6)∼BIT(10) will not change significantly, only BIT(11)∼BIT (16) will have obvious errors.…”

Section: Simulation Of the Optimized 5+5+6 Bits Capacitor Array Wimentioning

confidence: 99%

“…Recently, the rapid advancement of digital technology motivates the use of digital techniques especially for background algorithms. Background calibration corrects the error during the normal operation, which exists the possibility of non-convergence [10]. Averaging deal with the mismatch errors by performing multiple conversions of the same sample [11].…”

Section: Introductionmentioning

confidence: 99%

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Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Cen

Feng²,

Fan

et al. 2020

IEEE Access

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This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5+5+6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6µm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

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“…Therefore, BIT(1)∼BIT(6) meet the requirements of Equation (3). For BIT(1)∼BIT (10), it can also be easily obtained that BIT(1)∼BIT(10) meet the requirements of Equation (3).…”

Section: Overall Functionmentioning

confidence: 94%

Section: Overall Functionmentioning

confidence: 99%

Section: Simulation Of the Optimized 5+5+6 Bits Capacitor Array Wimentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Cen

Feng²,

Fan

et al. 2020

IEEE Access

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“…The MSB DAC calibration mechanism is uses a digital shuffling technique to identify mismatch by switching out different sets of capacitors that will only incur voltage fluctuation on V DAC in the presence of mismatch [15]. These errors are then amplified by A 1 after the SAR & QNF process and digitally tunes each MSB capacitor using a capacitive sub-DAC.…”

Section: Smp First a 1 Actively Samples Its Offset On The Top Plate Wmentioning

confidence: 99%

A 68μW 31kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR

Leene

Letchumanan

Constandinou

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noiseshaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18µm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM S of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 µW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm 2 area requirement.

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