A simple approach for designing online testable reversible circuits

Nayeem, Noor Muhammed; Rice, Jacqueline E.

doi:10.1109/pacrim.2011.6032872

Cited by 18 publications

(26 citation statements)

References 19 publications

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“…We have also noticed an average improvement of 48.80% in quantum cost, compared to the results reported in the initial version [27] of this approach. It is worth noting that our initial work was restricted only to a particular type of ESOP-based approach; thus we generally cannot expect better results than the results that we obtained from our initial work.…”

Section: Our Approachsupporting

confidence: 57%

“…Our approach builds on the idea initially presented in [27]. We consider a reversible circuit consisting only of Toffoli gates; in order to make such a circuit online testable, we add some CNOT gates and a parity line L which is initialized with a 0.…”

Section: Our Approachmentioning

confidence: 99%

“…Table III shows this very clearly. Previous work in [27] introduced an initial version of this approach which was limited to only reversible circuits generated by a particular synthesis approach. Not only have we extended the technique to any type of Toffoli gate cascade, but we have also found a significant improvement in terms of quantum cost.…”

mentioning

confidence: 99%

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Online Fault Detection in Reversible Logic

Nayeem

Rice

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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A new approach for online fault detection in Boolean reversible circuits is described. Previous work had described this approach for circuits generated by the basic ESOP-based logic synthesis, and in this work we extend the approach for any type of Toffoli networks. An online testable circuit is created by modifying an existing cascade of Toffoli gates in a simple process that involves changing the existing Toffoli gates as well as the addition of one line and 2p gates, where p is the number of lines in the original circuit.

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Section: Our Approachsupporting

confidence: 57%

Section: Our Approachmentioning

confidence: 99%

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Online Fault Detection in Reversible Logic

Nayeem

Rice

2011

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

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“…The addition of the testability features requires an average 491% overhead in the number of gates. However, as reported in [18], this is not an unreasonable amount, although the data reported there is restricted to Boolean reversible circuits. Furthermore the data in [18] also illustrates that a huge number of garbage outputs generally are required for the addition of online testability when working with reversible circuits; our approach requires no additional garbage outputs, and so is ahead of many of the strictly Boolean approaches in this regard.…”

Section: Discussionmentioning

confidence: 92%

On designing a ternary reversible circuit for online testability

Rahman

Rice

2011

Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

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Reversible logic has the potential to solve the energy efficiency problems that are beginning to create roadblocks in the continued advancement of today's computer systems. Multiple-valued versions of reversible logic can provide even further advantages, but the current literature contains very little work on testability of such designs. This paper details work on designing an online testable block for ternary reversible logic. We build on earlier work that introduced the basic design, and provide some improvements and modifications. This block implements most ternary logic operations and is capable of testing the reversible ternary network in real time (online). The block is built entirely of reversible building blocks, thus the block is itself reversible and so multiple such blocks can be combined to construct complete, testable, ternary reversible circuits.

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“…Online testing approaches for reversible circuits found in literature include testable circuits based on R 1 , R 2 and R 3 gates [19,20], based on testable reversible cells (TRCs) [21], based on online testable gates (OTGs) [22], dual-rail reversible gates [23,24], parity-preserving reversible gates [7,25,26] and based on extended toffoli gates (ETGs) [27,28] respectively. These approaches except ETG based [27,28] have been further categorized as parity-generating [19,20,21,22], parity-preserving [7,25,26] and dual rail online error detection methods [23,24]. According to results of [27,28], the approaches based on ETG are far superior to others in terms of quantum cost and garbage's generated.…”

Section: Related Workmentioning

confidence: 99%

An Extended Approach for Online Testing of Reversible Circuits

Jain¹,

Purohit²,

Jain³

2014

IOSRJCE

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Reversible computing has tremendous benefits in terms of power consumption, less heat dissipation and packaging density. Because its applications are found in diverse fields including quantum computing, nanotechnology, low power CMOS designs and cryptography, Reversible computing has gained attraction of many researchers recently. In order to incorporate fault testing capability in reversible circuits, a number of offline and online approaches have been proposed. In order to extend online testability of reversible circuits, an analysis followed by a Peres gate substitution is presented here. The proposed extension has identified online testing capabilities of MCF gates and has made all available libraries including MCT+MCF, MCT+P online testable. Furthermore a conversion for parity-preserving reversible circuits is presented. Finally the paper is concluded by proposing a generic online testable substitution of n*n reversible gate.

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A simple approach for designing online testable reversible circuits

Cited by 18 publications

References 19 publications

Online Fault Detection in Reversible Logic

Online Fault Detection in Reversible Logic

On designing a ternary reversible circuit for online testability

An Extended Approach for Online Testing of Reversible Circuits

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