A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Prégaldiny, F.; Lallement, Christophe; Mathiot, D.

doi:10.1016/s0038-1101(02)00248-4

Cited by 57 publications

(32 citation statements)

References 11 publications

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“…Work reported in the literature so far focused on C fringe to understand the scaling on L poly , gate oxide height, and gate height in the absence of contacts [4,5], and on parasitic capacitance contributions such as overlap and fringing [6]. Analytic approximations with optimization parameters have been used in [7], but ignore complex geometric and material effects in advanced CMOS transistors.…”

Section: Field Solver Simulationsmentioning

confidence: 99%

Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

Mueller¹,

Thoma²,

Demircan³

et al. 2007

Solid-State Electronics

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Section: Field Solver Simulationsmentioning

confidence: 99%

Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

Mueller¹,

Thoma²,

Demircan³

et al. 2007

Solid-State Electronics

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“…In general, C p is expressed as the sum of C of , C ov , and C if where C of is the outer fringing capacitance, C ov is the bias-dependent gate to source/drain overlap capacitance, and C if is the biasdependent inner fringing capacitance caused by the depletion region between the LDD(lightly doped drain) and poly Si gate [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Accurate RF C-V Method to Extract Effective Channel Length and Parasitic Capacitance of Deep-Submicron LDD MOSFETs

Lee

2015

JSTS:Journal of Semiconductor Technology and Science

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“…The parasitic capacitances are becoming an important issue for designing logic circuits wit h aggressive reduction of MOS transistor dimensions into the deep sub µm regime [1][2][3][4][5] . In digital applications, these parasitic capacitances have a very strong impact on propagation delay and the overall power dissipation of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Power Macro Modelling for CMOS Inverter of 0.12 um Technology

Naseem¹,

Riaz²,

Azam³

et al. 2013

Proceedings of the 2013 International Conference on Advanced Computer Science and Electronics Information

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-Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For dynamic power the voltage, capacitance and frequency are the major components of power dissipation. In this paper, we propose a power macro modelling technique for the CMOS inverter using 0.12µm technology. The dynamic power is directly linked with the load capacitance (C L ), and it is lumped as all internal parasitic capacitances. In our modelling, we take account of the parasitic capacitances with their dependence on channel length and width. Suitable values of other factors (i.e. threshold voltage V T , gate voltage V GS , drain voltage V DD etc.) are used for power consumption of the CMOS inverter.

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A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Cited by 57 publications

References 11 publications

Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

Accurate RF C-V Method to Extract Effective Channel Length and Parasitic Capacitance of Deep-Submicron LDD MOSFETs

Power Macro Modelling for CMOS Inverter of 0.12 um Technology

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