A simple technique to measure generation lifetime in partially depleted SOI MOSFETs

Abstract

This brief presents a new, simple method of measuring the generation lifetime in silicon-on-insulator (SOI)MOSFET's. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished Separation by IMplantation of OXygen (SIMOX) wafers and Bonded and Etchedback SOI (BESOI) wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and both the SIMOX and the BESOI are shown to have a lifetime variation of 610% across four inch wafers.

Compact Modeling of Weak Inversion Generation Transients in SOI MOSFETs

“…The weak inversion generation transient regime in a double-gate floating-body PD SOI MOSFET is observed when biasing one gate in the subthreshold region and by applying a step-function which drives the opposite gate into accumulation. [1][2][3] The induced charge nonequilibrium results in a drain current transient, which essentially reflects electron-hole pair generation in the extension of the generation region. Figure 1 shows weak-inversion drain current undershoots measured on n-MOSFET PD SOI devices with different gate lengths and film thickness t Si ϭ 200 nm, gate oxide thickness t ox1 ϭ 17 nm, buried oxide thickness t ox2 ϭ 100 nm, average channel doping N A ϭ 3.2 ϫ 10 17 cm Ϫ3 , and channel width Z ϭ 1 m. A similar generation transient is obtained when switching the front gate from strong or moderate inversion into weak inversion ͑part of a typical switching off regime͒.…”

“…Particularly, silicon-on-insulator ͑SOI͒ transistors appear to be extremely adapted for such low-current/low-voltage bias regimes for which there is a real lack of accurate compact models. 1 This paper deals with the critical compact modeling of the transient regimes of floating-body, partially depleted ͑PD͒ SOI MOS-FETs ͑weak and moderate inversions͒ induced by the step-functions applied on one of the transistors gates because the opposite is kept at constant bias. 2,3 The induced ''generation'' transient is analytically modeled in two different switching regimes that correspond to: ͑i͒ real transistor operation switching ͑on to off state͒ and (ii) to a characterization-dedicated method ͑similar to the deep-depletion pulsing͒.…”

High Soft-Error Tolerance Body-Tied Silicon-on-Insulator Technology with Partial Trench Isolation

“…The drift-diffusion model that includes Poisson's equation and the current-continuity equations was used in this numerical simulation. The carrier lifetime was set as 0.4 ms. 18,19) By using 4 Mbit SOI static random-access memories (SRAMs) with the PTI structure, soft-error testing was performed to investigate the effects of SOI thickness and well resistance. The partially depleted SOI devices were fabricated by using 0.18 mm process technology.…”

Estimating Temperature Dependence of Generation Lifetime Extracted from Drain Current Transients

“…9 Defining T 0 as the transient time for I d ͑t͒ to reach 90% of its steady-state value and using Eq. 1-3, the generation lifetime ͑ g ͒ can be obtained 10 as shown in Eq. 5…”

“…Floating body partially depleted ͑PD͒ SOI MOSFETs exhibit drain current transients [6][7][8][9] that can be used to determine the generation lifetime g without numerical analysis. 10 In this respect, it is important to remark that the real operation temperature of deep submicrometer transistors because self-heating in circuits is in the range of 80-100°C rather than room temperature.…”