A Simulation Framework for the Analysis of the TLB Behavior in Virtualized Environments

Venkatasubramanian, Girish; Figueiredo, Renato; Illikkal, Ramesh; Newell, Don

doi:10.1109/mascots.2010.30

Cited by 5 publications

(7 citation statements)

References 24 publications

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“…It shows more than 10 times execution time without a sidecore. This is due to frequent domain switches and contention of shared resources like caches and TLBs [8], [16], [18].…”

Section: A I/o Virtualizationmentioning

confidence: 99%

“…If the size of a second level cache can be reduced, transistors, die area and energy would be saved. However, previous study suggested that a large cache (4 MB) is a desired feature for VM I/O processing [16]. This is because their study simulated a virtualized system that did not have a dedicated core for VM I/O tasks.…”

Section: B Cache Organization A) First Level Cachementioning

confidence: 99%

“…There are some studies about caches, TLBs, and hardware prefetch in a virtualized environment [15], [16], [18], [34]. They studied the micro-architectural behaviour when all cores are shared among the control domain and guest VMs, thus the cache, TLBs, hardware data prefetch are significantly affected by guest VMs and applications.…”

Section: Related Workmentioning

confidence: 99%

“…Many studies explored micro-architectural behaviour of virtualized systems [15], [16], but they studied the behaviour when the I/O processing and guest VMs ran on shared cores, but our study focuses on the case where VM I/O tasks are off-loaded to a separate core.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

How Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization

Lee

Strazdins

2015

2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium

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I/O processing in virtualization is expensive. It significantly slows down application performance running on virtual machines due to frequent context switches and resource contentions. There are several methods to address the problem. One solution is the side-core approach to carry out virtualization I/O processing on a dedicated core, which offers close to baremetal performance, without sacrificing important virtualization features.Although the number of cores is continually increasing and the financial cost per core is dropping, considering the characteristics of I/O processing, the side-core approach can be more efficient with an asymmetric multi-processor (AMP) rather than a symmetric multi-processor (SMP).However, no thorough study has been performed to identify the requirements for the AMP to off-load the virtualization I/O tasks. In this paper, we examine various processor features, study behaviour of three different processors, and identify the most cost-efficient parameters for a side-core, both in terms of the financial cost and the number transistors.From our experimental analysis, we conclude that a narrow, fast (high clock) in-order pipeline, with small first/second level caches without hardware data prefetch, and a simple branch prediction unit are the desired features in a dedicated sidecore for I/O processing. We estimate that this small side-core should consist of one fourth the transistor budget and perform I/O processing with only a 10% performance loss at the same frequency, compared to a big side-core.

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“…It shows more than 10 times execution time without a sidecore. This is due to frequent domain switches and contention of shared resources like caches and TLBs [8], [16], [18].…”

Section: A I/o Virtualizationmentioning

confidence: 99%

Section: B Cache Organization A) First Level Cachementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

How Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization

Lee

Strazdins

2015

2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium

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show abstract

“…And the TLB entries would be swap out regularly. However, according to the locality principle [8,9], the TLB entries may be accessed again after being swapped out [10]. Thus, it is essential to store the TLB entries which are swapped out.…”

Section: B Tlb Emulationmentioning

confidence: 99%

An Emulation Model of IA-32 Memory Management

Chen

Jiang

Dong

et al. 2011

2011 International Conference on Intelligence Science and Information Engineering

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System emulation provides a new solution for software migrating on heterogeneous platform. As one of the important components of system emulation, memory emulation directly affects the performance of system. This paper presents a universal emulation model of IA-32 memory management with Software MMU, virtual TLB and virtual MMIO. And an IA-32 memory management emulator prototype is implemented successfully on the Alpha platform which achieves about 10% of the host machine's performance presently. Compared to Bochs, the performance of our emulator has increased by about 17 percent.

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Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

Gong

2021

IEEE Access

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Monolithic 3D (M3D) integration has been emerged as a promising technology for finegrained 3D stacking. As the M3D integration offers extremely small dimension of via in a nanometer-scale, it is beneficial for small microarchitectural blocks such as caches, register files, translation look-aside buffers (TLBs), etc. However, since the M3D integration requires low-temperature process for stacked layers, it causes lower performance for stacked transistors compared to the conventional 2D process. In contrast, non-volatile memory (NVM) such as magnetic RAM (MRAM) is originally fabricated at a low temperature, which enables the M3D integration without performance degradation. In this paper, we propose an energy-efficient unified L2 TLB-cache architecture exploiting M3D-based SRAM/MRAM hybrid memory. Since the M3D-based SRAM/MRAM hybrid memory consumes much smaller energy than the conventional 2D SRAM-only memory and 2D SRAM/MRAM hybrid memory, while providing comparable performance, our proposed architecture improves energy efficiency significantly. Especially, as our proposed architecture changes the memory partitioning of the unified L2 TLB-cache depending on the L2 cache miss rate, it maximizes the energy efficiency for parallel workloads suffering extremely high L2 cache miss rate. According to our analysis using PARSEC benchmark applications, our proposed architecture reduces the energy consumption of L2 TLB+L2 cache by up to 97.7% (53.6% on average), compared to the baseline with the 2D SRAM-only memory, with negligible impact on performance. Furthermore, our proposed technique reduces the memory access energy consumption by up to 32.8% (10.9% on average), by reducing memory accesses due to TLB misses.

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A Simulation Framework for the Analysis of the TLB Behavior in Virtualized Environments

Cited by 5 publications

References 24 publications

How Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization

How Small Can it Be?: The Design of a Cost-Effective Side-core for I/O Virtualization

An Emulation Model of IA-32 Memory Management

Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture

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