A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

Ukita, M.; Murakami, Shuji; Yamagata, T.; Kuriyama, H.; Nishimura, Yasumasa; Anami, Keiko

doi:10.1109/4.245590

“…In this case also the delay contribution of each component is balanced. The same conclusion can be reached from state-of-the-art SRAM designs [15,26,27]. Moreover, it is reasonable to expect that these contributions will continue to be balanced, because a well-balanced and optimised memory design cannot be fully dominated by the energy or delay of one of its components.…”

Section: E-sram Modelmentioning

confidence: 50%

Global interconnect trade-off for technology over memory modules to application level

Papanikolaou

¹

,

Miranda

²

,

Catthoor

³

et al. 2003

Proceedings of the 2003 International Workshop on System-Level Interconnect Prediction

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In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained at that level, we can exploit it to make the switching on the interconnect wires slower and thus less energy consuming. In this way, we have shown that for real-life applications the power consumption at future technology nodes can be reduced by about 34%, when compared to the option provided by the ITRS roadmap. This is achieved by, instead of using the very fast and power hungry wires, selectively using slower and thinner interconnect wires while still meeting the application real-time constraints.

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“…Another possible write pattern is 1->0, which is considerably difficult in single-bitline configuration because it presents conditions similar to that of the read mode. Boosted wordline technique [1] is a traditional solution to this problem, but it potentially induces the unreliable read and hardware overheads. Instead of the boosted wordline technique, the SWDR cell uses a tail transistor N3 to facilitate writing node B from low to high.…”

Section: Write '1' Modementioning

confidence: 99%

“…The contributions of the proposed SWDR cell are as follows. (1) Unlike the conventional SRAM cell where the power dissipated in both writing '0' and '1' are the same, the SWDR cell can prevent the single write bitline from being discharged if the written value is '0'. Therefore, the write '0' power is far less than the write '1' power in the SWDR cell.…”

Section: Introductionmentioning

confidence: 98%

“…(2) Writing cell state from low to high is considerably difficult in single-bitline configuration because it presents conditions similar to that of the read mode. Instead of the traditional boosted wordline technique [1], the SWDR cell uses a tail transistor to disconnect the pull-down path, such that writing cell state to high is easy to be achieved.…”

Section: Introductionmentioning

confidence: 99%

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A power-aware SWDR cell for reducing cache write power

Chang

¹

,

Yang

²

,

Lai

³

2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

2

0

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Low power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%~92% reduction in average cache write power dissipated in bitlines.

show abstract

“…(2) Writing cell state from low to high is considerably difficult in single-bitline configuration because it presents conditions similar to that of the read mode. Instead of the traditional boosted wordline technique [1], the SWDR cell uses a tail transistor to disconnect the pull-down path, such that writing cell state to high is easy to be achieved.…”

Section: Introductionmentioning

confidence: 99%

A power-aware SWDR cell for reducing cache write power

Chang

¹

,

Yang

²

,

Lai

³

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

0

View full text Add to dashboard Cite

Low power caches have become a critical component of both hand-held devices and high-performance processors. Based on the observation that an overwhelming majority of the data written to the cache are '0', in this paper we propose a power-aware SRAM cell with one single-bitline write port and one differential-bitlines read port, called SWDR cell, to minimize the cache power consumption in writing '0'. The SWDR cell uses a circuit-level technique, which is software independent and orthogonal to other low power techniques at architecture-level. Compared to the conventional SRAM cell, the experimental results show that without compromise of both performance and stability, the SWDR cell can result in 73%~92% reduction in average cache write power dissipated in bitlines.

show abstract

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

Cited by 24 publications

References 4 publications

Global interconnect trade-off for technology over memory modules to application level

Global interconnect trade-off for technology over memory modules to application level

A power-aware SWDR cell for reducing cache write power

A power-aware SWDR cell for reducing cache write power

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