Proceedings of the 2003 International Workshop on System-Level Interconnect Prediction 2003
DOI: 10.1145/639929.639954
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Global interconnect trade-off for technology over memory modules to application level

Abstract: In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained … Show more

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Cited by 9 publications
(3 citation statements)
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“…Separate, complementary methodologies can be used, in addition to our work, to reduce the energy of the instruction memory [4]. In the context of this paper, the energy estimations are calculated using the model in [25] and concern the energy dissipated by the memory. This model depends on memory footprint factors (i.e., memory size, internal structure of banks and sub-banks, memory leaks, working time of the memory and technology) and energy consumption factors created by memory accesses (i.e., number of memory accesses, energy consumption in active mode, size of the memory and technology).…”
Section: Dynamic Data Type Search Spacementioning
confidence: 99%
“…Separate, complementary methodologies can be used, in addition to our work, to reduce the energy of the instruction memory [4]. In the context of this paper, the energy estimations are calculated using the model in [25] and concern the energy dissipated by the memory. This model depends on memory footprint factors (i.e., memory size, internal structure of banks and sub-banks, memory leaks, working time of the memory and technology) and energy consumption factors created by memory accesses (i.e., number of memory accesses, energy consumption in active mode, size of the memory and technology).…”
Section: Dynamic Data Type Search Spacementioning
confidence: 99%
“…No accesses to instruction memories are measured in this paper since we do not focus on any concrete architecture and moreover the data accesses are the most important factor to optimize for new dynamic applications [7]. Finally, the energy estimations are made with the use of an updated version of the CACTI model [17]. This is a complete energy/delay/area model for embedded SRAMs that depends on memory usage factors (e.g., size, internal structure or leaks) and factors originated by memory accesses (e.g., number of accesses or technology node used).…”
Section: Automated Pareto-optimal Configurations Selectionmentioning
confidence: 99%
“…Then, we automatically keep the combinations, which have the lowest energy consumption, shortest execution time, lowest memory footprint and lower memory accesses. The energy estimations are calculated using an updated version of the CACTI model [12]. According to our experimental results (Section 4) approximately 80% of the DDT combinations produce not optimal results for all the aforementioned metrics.…”
Section: Application-level Ddt Explorationmentioning
confidence: 99%