A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology

Abbasian, Erfan; Gholipour, Morteza; Birla, Shilpi

doi:10.1007/s13369-022-06821-6

Cited by 20 publications

(4 citation statements)

References 33 publications

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“…Complementary metal‐oxide‐semiconductor (CMOS) technology scaling has become the main key to continuous progress in the silicon‐based semiconductor industry over the past three decades. However, as the technology scaling enters beyond 32 nm regime, CMOS devices face many serious problems such as increased leakage currents, difficulty with an increase in ON ‐current, large parametric variations, low reliability, increase in manufacturing cost, etc 6–10 . So, there is a need to look for different potential alternatives to CMOS.…”

Section: Introductionmentioning

confidence: 99%

“…However, as the technology scaling enters beyond 32 nm regime, CMOS devices face many serious problems such as increased leakage currents, difficulty with an increase in ON-current, large parametric variations, low reliability, increase in manufacturing cost, etc. [6][7][8][9][10] So, there is a need to look for different potential alternatives to CMOS. It is found that carbon nanotube field-effect transistors (CNTFET) and graphene nanoribbon field-effect transistors (GNRFET) have a higher power of switch, curves with more ideal voltage, and better mobility, consequently, they can be favorable replacements for CMOS.…”

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confidence: 99%

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An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

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SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

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Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

Circuit Theory & Apps

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show abstract

“…8 The extended CMOS devices comprise nanowire field effect transistors(nanowire FET), 15 Carbon nanotube field effect transistors (CNTFET), 16 graphene nano-ribbon field effect transistors (GNRFET), 17 negative-capacitance field-effect transistor (NC-FET), 18 Spin field effect transistor (SPIN FET) 19 etc.. However, the beyond CMOS devices include Fin Shaped Field Effect Transistor (FinFET), 20 Tunnel field effect transistor (TFET) [21][22][23][24][25] etc.…”

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confidence: 99%

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

Sachdeva

Sharma

Gupta

et al. 2023

ECS J. Solid State Sci. Technol.

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Higher charge mobility, gate control, and better electrostatics are the key reasons that make a carbon nanotube field effect transistor (CNTFET) a better candidate as the successor of conventional complementary metal oxide semiconductor transistors. However, the increased charge mobility also enhances the leakage power. This work uses CNTFET for designing a low-power eight-transistor static random access memory (8T SRAM) cell. The leakage power of the proposed cell is reduced by 2.21× compared to conventional 6T SRAM at 0.3 V with similar CNTFET parameters. The read and write power delay product of the proposed design is improved by 1.02× and 1.85×, respectively. Moreover, the read/write/ hold static noise margin of the proposed cell is also enhanced by 1.98×/ 0.99×/ 1.01×, respectively, compared to the conventional 6T design. The proposed cell is also compared with three already proposed CNTFET based 8T SRAM designs. Cadence Virtuoso simulation tool and Stanford University 32 nm CNTFET verilog-A model file are used to achieve simulation results.

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“…[4][5][6][7] These problems reduce the suitability of the MOSFET for power/energy-efficient applications. 5 In response, researchers have proposed various new alternative solutions and technologies to traditional MOSFET technology, such as fin-based FET (FinFET), [8][9][10][11][12][13][14] carbon nanotube-based FET (CNTFET), 6,7,15,16 and graphene nanoribbon-based FET (GNRFET). 4,[17][18][19] Among these emerging technologies, GNRFET offers excellent properties and is compatible with existing silicon-based MOSFET, and is an attractive option for achieving higher performance and efficiency in future electronic devices.…”

mentioning

confidence: 99%

A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

Rohani,

Emrani Zarandi

2023

ECS J. Solid State Sci. Technol.

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To address interconnections and energy issues associated with binary logic, designers are increasingly turning to ternary logic. One effective approach to implementing ternary logic-based circuits is to use a multiple-threshold voltage (multi-Vth) design. In particular, graphene nanoribbon (GNR)-based field-effect transistors (GNRFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology for sub-32nm feature sizes, as GNRs have excellent properties that can overcome scaling issues in CMOS. This paper introduces a ternary multiplier implemented with 32 nm GNRFET technology, which demonstrates high efficiency with only 26 transistors. Simulation results show that the proposed multiplier improves power dissipation and product-delay-power (PDP) by at least 37.30% and 22.22%, respectively, compared to existing multiplier designs when run at 0.9V. Moreover, our proposed design is implemented with a carbon nanotube-based FET (CNTFET) technology. The GNRFET-based multiplier improved power and PDP by 41.77% and 30%, respectively in the cost of increasing the delay by 25%, compared to its CNTFET-based equivalent. Finally, we analyze the proposed multiplier under the process and environmental parameters variations of GNRFET technology. Overall, our results demonstrate the advantages of using GNRFET technology for implementing ternary logic-based circuits and provide insight into the impact of different design choices on performance.

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A Single-Bitline 9T SRAM for Low-Power Near-Threshold Operation in FinFET Technology

Cited by 20 publications

References 33 publications

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

A CNTFET Based Bit-Line Powered Stable SRAM Design for Low Power Applications

A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

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