A Single Slope ADC With Row-Wise Noise Reduction Technique for CMOS Image Sensor

Nie, Kaiming; Zha, Wanbin; Shi, Xiaolin; Li, Jiawen; Xu, Jiangtao; Ma, Jan

doi:10.1109/tcsi.2020.2979321

Cited by 46 publications

(17 citation statements)

References 14 publications

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“…In contrast, the dark spots in B-region are eliminated while maintaining the original image quality. Table I compares the performance of the current study with recently published works [17,30,31,32]. For a fair performance comparison, the figure of merits (FoMs) are calculated according to [33,34].…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Black-sun noise immune correlated double sampling scheme for CMOS image sensors

Lee

Kim

2021

IEICE Electron. Express

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This paper presents a black-sun immune correlated double sampling (CDS) scheme for high-quality imaging. Based on an analysis of signal characteristics in strong light conditions, a clamping circuit-based signal difference generator is proposed to accurately present the bright light information. The proposed scheme eliminates the black-sun noise with simple circuitry to improve the A/D conversion efficiency. Moreover, it can be is reversible to the conventional algorithm so that it still preserves the structural advantages of the existing CMOS image sensor (CIS) structure. A prototype CIS with a column-parallel 11-bit single-slope (SS) analog-todigital converter (ADC) was fabricated in a 0.11-μm 1P4M CIS process with a 2.9-μm pixel pitch.

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Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Black-sun noise immune correlated double sampling scheme for CMOS image sensors

Lee

Kim

2021

IEICE Electron. Express

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“…When the pixel signal decreases according to its own light intensity, it causes fluctuations through the globally shared biasing lines V BIAS1 and V rBIAS2 in the adjacent columns (i.e., coupling noise). Thus, the column bias sampling (CBS) technique [23], [24] is adopted to alleviate the effects of coupling noise. In this study, the LBC scheme is proposed to minimize the power consumption of each column during the T CO period while reducing the bias currents of the pixel SFs.…”

Section: Proposed Readout Schemementioning

confidence: 99%

A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure

Hyeon

Kim

2022

IEEE J. Electron Devices Soc.

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This paper presents a low-power multiple-column-parallel (MCP) readout CMOS image sensor (CIS) in terms of its structural features. Because each column in an MCP unit performs analogto-digital (A/D) conversion sequentially, the columns have their own operating periods before and after A/D conversion. Upon completion of A/D conversion in each column, a local bias control (LBC) scheme is applied using a bias circuit of a pixel source follower (SF) to minimize power consumption. In this study, the effectiveness of the proposed LBC scheme is verified for the MCP readout structure. Through simple modification of a column-biasing circuit, the prototype MCP readout CIS achieved significant power savings, which shows its applicability to low-power CIS applications. The prototype CIS was implemented using a 1P6M 0.18-µm CMOS process. A maximum frame rate of 430 fps was achieved while consuming 2.38 mW of power. Compared to a conventional column driver, the proposed LBC scheme reduces the total power consumption by 29.4%, which is an overall power savings of 15%. The prototype CIS also demonstrated figures of merit of 119.1 µV•nJ and 8 µV rms /kHz. INDEX TERMS CMOS image sensor (CIS), pixel source follower, column driver, bias voltage control technique, local bias control (LBC) scheme, multiple-column-parallel (MCP) readout.JANG-SU HYEON (Student Member, IEEE) received the B.S. degree from the

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“…The power consumption of this work is not best, mainly owing to the high supply voltage of 3.3 V using in the first pre-amplifier of the comparator. Due to the usage of the delay chain in each column ADC, the area of the proposed ADC is slightly larger than the designs in [7,17]. However, through the foreground calibration and proposed CDS operation, this TS-SS ADC realizes an excellent trade-off among readout speed, silicon area and power consumption.…”

Section: B Post-layout Simulationmentioning

confidence: 99%

“…This necessarily increases the conversion speed of each column ADC. Therefore, multiple types of column-parallel ADC architectures have been employed to increase the sampling rate, such as successive approximate register (SAR) ADCs [1][2][3][4], cyclic ADCs [5,6], and single-slope (SS) ADCs [7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

Zhang

Ning

et al. 2020

IEEE Access

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This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-todigital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm 2 and the power consumption is 72 μW. INDEX TERMS Column-parallel ADC; single-slope (SS) ADC; two-step ADC; foreground calibration

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A Single Slope ADC With Row-Wise Noise Reduction Technique for CMOS Image Sensor

Cited by 46 publications

References 14 publications

Black-sun noise immune correlated double sampling scheme for CMOS image sensors

Black-sun noise immune correlated double sampling scheme for CMOS image sensors

A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure

A 12-Bit Column-Parallel Two-Step Single-Slope ADC With a Foreground Calibration for CMOS Image Sensors

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