A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Drive Development

Judge, Paul D.; Mathieson, Ross; Finney, S.J.

doi:10.1109/ecce-asia49820.2021.9479081

Cited by 8 publications

(5 citation statements)

References 15 publications

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“…This paper aims to empirically assess, due to the lack of suitable nanosecond scale simulation models, the influence of these AGD capabilities on a 1200 V 400 A SiC half bridge module's switching performance in terms of energy loss, V DS /I D overshoot and V DS /I D oscillation. This was performed with an AGD referred to as the Modular Multilevel Gate-Driver (MMGD), which was capable of modulating its output voltage in 5 V increments from -5 V to 15 V, with a resolution of 2.5 ns as presented in [11]. This was used as a tool to generate the gate signal patterns studied in this investigation and is not considered a viable AGD for industrial applications due to its high cost and complexity.…”

Section: Gate Drivermentioning

confidence: 99%

“…The AGD's presented in the literature vary widely in their GTR, with typical values being in the region of 20-40 ns [21]- [25]. Greater GTR require the use of faster controller clock speeds which can be harder to implement, often requiring additional chips, an example being the MMGD presented in [11], which used a 200 MHz FPGA with an additional clock divider to give a GTR of 2.5 ns. Higher GTR of up to 100 ps have been demonstrated in the literature with custom ASIC designs, though these focused on Gallium Nitride (GaN) MOSFET's [26].…”

Section: Gate Timing Resolutionmentioning

confidence: 99%

“…As discussed in the introduction, this study utilised the Modular Multi-Level Gate Driver (MMGD), shown in Fig. 3 and presented in the publication [11], to perform investigations into how the GTR and output stage complexity influenced the achievable switching performance of SiC MOSFET modules. Its design was driven to be used as a highly flexible research tool that can be used to investigate various different gatedrive strategies, not as a practical solution for industrial applications.…”

Section: F Modular Multi-level Gate Driver (Mmgd)mentioning

confidence: 99%

“…A frequency doubling circuit that utilises programmable delay chips was used to increase the effective clocking frequency to 400 MHz, from the 200 MHz clock used internally within the FPGA, giving the MMGD a GTR of 2.5 ns. Additional details of the MMGD's design process and capabilities can be found in the publication [11], where it was first introduced.…”

Section: F Modular Multi-level Gate Driver (Mmgd)mentioning

confidence: 99%

See 3 more Smart Citations

Investigation Into Active Gate-Driving Timing Resolution and Complexity Requirements for a 1200 V 400 A Silicon Carbide Half Bridge Module

Parker

Şahin

Mathieson

et al. 2023

IEEE Open J. Power Electron.

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Silicon Carbide MOSFETs have lower switching losses when compared to similarly rated Silicon IGBT, but exhibit faster switching edges, larger overshoots and increased oscillatory switching behaviour, resulting in greater electro-magnetic interference (EMI) generation. Active Gate Drivers (AGD) can help mitigate these issues while maintaining low switching losses. Numerous AGD topologies have been presented with varying capabilities in terms of timing resolution and output stage complexity. This paper presents an experimental investigation into the influence these capabilities have on the switching performance of an AGD driven high current module, with the goal of advising future AGD designers on the performance trade-offs between signal resolution and complexity. A 2.5 ns resolution 6-level AGD was utilised in combination with parameter sweeps and a genetic algorithm to determine gate voltage patterns that provided improved switching performance. Results indicate that higher resolution (2.5-5 ns) provided the greatest improvements in switching performance, even utilising the simplest considered gate driving patterns, with the use of more complex patterns offering minimal additional improvements. However, at lower timing resolutions (10-40 ns) a stronger set-point dependence degradation in switching performance is observed when using simpler gate patterns, which can be mitigated by utilising more complex patterns.

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Section: Gate Drivermentioning

confidence: 99%

Section: Gate Timing Resolutionmentioning

confidence: 99%

Section: F Modular Multi-level Gate Driver (Mmgd)mentioning

confidence: 99%

Section: F Modular Multi-level Gate Driver (Mmgd)mentioning

confidence: 99%

See 2 more Smart Citations

Investigation Into Active Gate-Driving Timing Resolution and Complexity Requirements for a 1200 V 400 A Silicon Carbide Half Bridge Module

Parker

Şahin

Mathieson

et al. 2023

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

show abstract

“…The fundamental idea of AGD is to control the slew rate of the power device actively during the switching transient to suppress unwanted overshoots in device voltage/current and resulting EMI, while achieving a fast switching. This can be done either by actively changing the gate resistance [4,5,7,8], applying a variable gate-source voltage (V GS ) [6,[9][10][11][12][13][14], or limiting/boosting the gate current [15][16][17]. Initially proposed to drive Si IGBTs [11,15], AGD has been intensely studied for SiC MOSFETs in recent years, with typically nano-second order control due to the increased switching speed.…”

Section: Introductionmentioning

confidence: 99%

Digital-Twin-Compatible Optimization of Switching Characteristics for SiC MOSFETs Using Genetic Algorithm

Takayama

Fukunaga

Hikihara

2023

IEEE J. Emerg. Sel. Top. Ind. Electron.

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Active gate drive (AGD) is one of the key techniques to utilize SiC power devices' fast-switching capability without compromising the drawbacks. However, the increasing complexity in the circuit design makes it hard to have an optimized operation without expert know-hows or considerable design efforts. This paper demonstrates a digital-twincompatible metaheuristic optimization system for a digital AGD. It offers a totally-digital control of switching characteristics of power devices through genetic-algorithm-based optimization. An individually developed digital AGD is adopted to generate a genetically expressed gate-voltage waveform by a multi-bit gate signal sequence. The optimization system is verified in simulation and experiment by successfully obtaining the optimum Pareto-front solutions, which clarify the relationship between the selected gate voltage levels and the device characteristics. The optimization is also performed for variable operating conditions and for different SiC MOSFETs. The results of this paper offer feasibility for a software-based optimization of gate drive design.

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Investigation into active‐gate‐driving performance and potential closed‐loop controller implementations for silicon carbide MOSFET modules

Şahin,

Parker,

Mathieson

et al. 2024

IET Power Electronics

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Active gate driving (AGD) is a promising concept for achieving high‐performance power transistor switching. This is particularly crucial for Silicon Carbide (SiC) MOSFETs since their inherently fast switching characteristics give rise to severe overshoots and oscillations which translate into increased levels of electromagnetic interference (EMI) emissions. In this paper, an AGD strategy using a single‐pulse applied during the switching transient is considered for a 1200 V 400 A SiC MOSFET module. The effect of single‐pulse timing, load current, and temperature on the switching performance is analyzed in detail. The radiated EMI reduction benefits are quantified by H‐field and E‐field probes. A conceptual closed‐loop AGD approach is presented and compared to open‐loop operation. For the transistor turn‐off case under full load current of 400 A, experimental results show that it is possible to reduce voltage overshoot by 43.3%, voltage and current oscillations by 69.7% and 52.2% respectively, and EMI by 76.6%, with a trade‐off in the switching energy by a relatively minor increase of 18.2%, compared to the conventional gate driving case. For the turn‐on case, current overshoot was reduced by 32.7%, EMI by 52%, voltage and current oscillations by 54.6% and 52.8%, respectively, with a penalty of 50.9% increase in the switching loss.

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A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Drive Development

Cited by 8 publications

References 15 publications

Investigation Into Active Gate-Driving Timing Resolution and Complexity Requirements for a 1200 V 400 A Silicon Carbide Half Bridge Module

Investigation Into Active Gate-Driving Timing Resolution and Complexity Requirements for a 1200 V 400 A Silicon Carbide Half Bridge Module

Digital-Twin-Compatible Optimization of Switching Characteristics for SiC MOSFETs Using Genetic Algorithm

Investigation into active‐gate‐driving performance and potential closed‐loop controller implementations for silicon carbide MOSFET modules

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