A SmartBIST variant with guaranteed encoding

Koenemann, B.; Barnhart, C.; Keller, B.; Snethen, T.; Farnsworth, O.; Wheater, D.L.

doi:10.1109/ats.2001.990304

Cited by 226 publications

(109 citation statements)

References 6 publications

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“…Most use special decompression hardware on the chip [2,3,9,10,12,16]. In this paper, we focus on software-based test data compression techniques that are applicable to deterministic test vectors since the test vectors for a core in a SoC are usually precomputed by the vendor.…”

Section: Introductionmentioning

confidence: 99%

Matrix-based software test data decompression for systems-on-a-chip

Balakrishnan

Touba

2004

Journal of Systems Architecture

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This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the processorÕs on-chip memory. The processor executes a program which decompresses the data and applies it to the scan chains of each core-under-test. The matrix-based operations that are used to decompress the test vectors can be performed very efficiently by the embedded processor thereby allowing the decompression program to be very fast and provide high throughput of the test data to minimize test time. Experimental results demonstrate that the proposed approach provides greater compression than previous methods.

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Section: Introductionmentioning

confidence: 99%

Matrix-based software test data decompression for systems-on-a-chip

Balakrishnan

Touba

2004

Journal of Systems Architecture

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“…The problem of compacting a set of test sequences for sequential circuits was modeled with the help of a covering matrix, where the test sequences can be modeled as columns with variable cost to reflect the cost (number of vectors) of covering selected subsets of circuit faults [6]. D-algorithm that is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions [11]. PODEM algorithm is a new test generation algorithm for combinational logic circuits.…”

Section: Introductionmentioning

confidence: 99%

Test Compaction of Logic Blocks by using Fault Identification Method

Vardhan¹,

Sathiskumar²

2015

International Journal of Advanced Research in Computer and Comm

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An arbitrary design implemented into a field-programmable gate array (FPGA). FPGA contains many logical blocks. Fault equivalence and fault dominance method are used to detect the fault with minimum time period. An approach provides transparent scan to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable. It uses n number of test configuration instead of 2 n number of test configuration by test code algorithm. Transparent scan enhances the ability to produce a compact test set for a group of logic blocks. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it chooses a subset that finds all the target faults, which are propagated by the complete set by using Modelsim and area is obtained by using the XILINX ISE 8.1 software.

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“…Therefore, the system integrator is restrained from using TDC methods which may require automated test pattern generation (ATPG) integration. For these reasons, in [11] the XOR − Network approach from [2] has been tailored for core based SoC test. In the remainder of this paper we will use the XOR − Network method as introduced in [11], and, in order to avoid confusion, we will refer to this particular implementation as XNet.…”

Section: Preliminaries and Motivationmentioning

confidence: 99%

“…TDC has been approached from a number of research directions. For example, methods which (i) exploit the sparseness of care bits in the test set have been proposed in [2,6,17], and methods which (ii) exploit the regularities within the test set have been proposed in [5,12,18,21].…”

Section: Introductionmentioning

confidence: 99%