13th Asian Test Symposium
DOI: 10.1109/ats.2004.15
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A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA

Chin-Lung Chuang
1
,
Deng-Fong Lu
2
,
C.-N.J. Liu
3
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Cited by 7 publications
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Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor

Penttinen
1
,
Jastrzębski
2
,
Pollanen
3
et al.
2006 IEEE Design and Diagnostics of Electronic Circuits and Systems
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Run-Time Debugging and Monitoring of FPGA Circuits Using Embedded Microprocessor

Penttinen
1
,
Jastrzębski
2
,
Pollanen
3
et al.
2006 IEEE Design and Diagnostics of Electronic Circuits and Systems
3
0
0
0
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A scalable hybrid verification system based on HDL slicing

Banerjee1,
Gupta2,
Jain3
2011
2011 IEEE International High Level Design Validation and Test Workshop
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The third generation verification technology based SOC debugging

Ruan
1
,
Li
2
,
Song
3
et al. 2011
2011 International Conference on Computational Problem-Solving (ICCP)
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