A soft error vulnerability analysis framework for Xilinx FPGAs

Sari, Aitzan; Agiakatsikas, Dimitris; Psarakis, Mihalis

doi:10.1145/2554688.2554767

Cited by 18 publications

(11 citation statements)

References 9 publications

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“…The toolkit offers a rich Application Programming Interface (API) to parse, analyse and manipulate XDL files (which can be easily created from Xilinx netlists). A very recent work that makes use of this toolkit is presented in [Sari et al 2014]. In this paper, the authors estimate the susceptibility of an FPGA design.…”

Section: Mitigation Design Techniques Aimed At Design-time Fault Avoimentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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Section: Mitigation Design Techniques Aimed At Design-time Fault Avoimentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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“…For the error rates, we use CREME96 to predict the error rate of a configuration bit for each device in the same orbit as the EO-1 satellite from our case study mission. We calculate the error rate of each resource as the number of configuration bits used to program the resource times the error rate of a single configuration bit [12]. This is a worst-case estimation technique that assumes all bits associated with a resource are able to cause an error.…”

Section: -2 In Ternal-memory Ex Tensionmentioning

confidence: 99%

Memory-aware optimization of FPGA-based space systems

Wulf

George

Gordon‐Ross

2015

2015 IEEE Aerospace Conference

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Designing FPGA-based space systems that meet mission goals of high performance, low power, and high dependability is challenging. Our previous work established a framework to help designers of FPGA-based space systems to consider a wide range of designs, evaluate the power and dependability of those designs, and narrow the large design search space down to a significantly reduced Pareto-optimal set.To further improve and extend our framework's ability to evaluate and optimize increasingly complex aerospace systems, this paper details our framework's memory extension, which enables memory-aware analysis by refinements to our framework's original analysis. The memory-aware analysis more accurately predicts a system's power and dependability by modeling three memory resources: internal-memory capacity, internal-memory bandwidth, and external-memory bandwidth.We demonstrate the importance of our framework's memory extension by investigating a case study based on an enhanced version of a hyperspectral-imaging satellite mission. After analyzing 22 unique Virtex FPGA devices and optimizing each for power and then dependability, the framework selects four Pareto-optimal designs, ranging from very-low power to high dependability. Results of the framework's memory extension show that memory resources may limit the performance of an FPGA-based space-system design and contribute significantly towards power and dependability results.

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“…FPGAs are more vulnerable to SEUs compared to Application Specific Integrated Circuits (ASIC) [2]. In SRAM-based FPGAs, all programmable resources (particularly routing switches) are configured by SRAM cells; these devices are very susceptible to such errors [3].…”

Section: Introductionmentioning

confidence: 99%

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

Jahanirad¹

2018

IJCA

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Soft errors such as Single Event Upset (SEU) have great effect on performance degradation of circuits implemented on SRAM_based FPGA. The soft error in configuration bits which control the logic and routing parts of the circuit, leads to permanent faults. In this paper, we have developed a coevolutionary method to reduce the effect of soft error on the implemented circuit on FPGA. This method is based on cooperation of genetic algorithm and ant colony optimization. The efficiency of co-evolutionary method has been proved by comparison of its results with the proposed genetic algorithm and ant colony optimization. The experimental results for some MCNC benchmark circuits show up to 34% improvement compare to genetic algorithm and up to 60% improvement against ant colony optimization.

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A soft error vulnerability analysis framework for Xilinx FPGAs

Cited by 18 publications

References 9 publications

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Memory-aware optimization of FPGA-based space systems

Co-evolutionary Approach to Reduce Soft Error Rate of Implemented Circuits on SRAM_based FPGA

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