A software-based self-test and hardware reconfiguration solution for VLIW processors

Koal, Tobias; Vierhaus, Heinrich Theodor

doi:10.1109/ddecs.2010.5491821

Cited by 24 publications

(10 citation statements)

References 12 publications

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“…The most important issue is to create a SBST with a high fault coverage probability, which was already shown for very different architectures [15]. Reliability and MTTF improvement was possible for the chosen example in [14]. To reach a specific goal like maximizing reliability or MTTF, with or without a maximal hardware overhead, a very time consuming process is required.…”

Section: Architecturementioning

confidence: 97%

“…This section summarizes the basic built-in self repair (BISR) approach originally published in [14] for a very long instruction word (VLIW) processor. In figure 1 the VLIW architecture and their additional BISR components are depicted.…”

Section: Architecturementioning

confidence: 99%

“…A memory management unit (MMU) organizes load/store and data exchange operations between different clusters. To show the basic BISR approach in [14], a configuration with three clusters and three FUs per cluster was chosen as an example. Spare components were implemented in the following way:…”

Section: Architecturementioning

confidence: 99%

“…In [14] we presented a less hardware costly solution for handling redundancy for permanent fault compensation of logic cores, based on software test and reconfiguration. The basic issue of hardware redundancy techniques relies on the fact that additional hardware is also susceptible to faults.…”

Section: Introductionmentioning

confidence: 99%

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Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Koal

Vierhaus

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Reliability and the mean lifetime are major aspects in today's semiconductor device manufacturing. The continuous downscaling of transistor sizes and power supplies are the root causes of higher vulnerabilities of integrated circuits against time zero process variation, time dependent degradation and random faults induced by environmental influences like particle strikes. Handling permanent faults becomes inevitably a suitable solution to guarantee high reliabilities as well as increased lifetimes. Builtin self-repair is a possible solution, which exchanges faulty units with spare parts at the costs of extra hardware. In this paper, we evaluate the influence of different replacement strategies and their resulting additional hardware structures on reliability and mean lifetime. This analytical process allows to find the optimal replacement strategy for a given system, without implementing and synthesizing each case.

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Section: Architecturementioning

confidence: 97%

Section: Architecturementioning

confidence: 99%

Section: Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Koal

Vierhaus

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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“…The core partitioning process can be performed relatively easily in specific cores with identical parts, e.g. the VLIW processor [8] or the multiplier unit in the LEON processor [9]. Since these cores encompass numerous identical parts, they can simply be considered as FBs for further RLB implementation.…”

Section: A Core Partitioning Processmentioning

confidence: 99%

Built-in self-repair architecture generator for digital cores

Kristofik

Baláž

2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.

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Partition-Based Faults Diagnosis of a VLIW Processor

Sabena

Reorda

Sterpone

2015

IFIP Advances in Information and Communication Technology

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Reconfigurable systems are increasingly used in different domains, due to the advantages they offer in terms of flexibility: reconfigurability can also be used for managing possible faults affecting a circuit, when fault tolerance is the target. In this case the system must be able to (1) detect any possible fault, (2) identify the module (or partition) including it, and (3) take proper actions able to overcome the problem (e.g., by substituting the faulty module with a spare one). In this chapter, we address the point (2) when a Very Long Instruction Word (VLIW) processor is used by resorting to a Software-Based Self-Test (SBST) approach. SBST techniques have shown to represent an effective solution for permanent fault detection and diagnosis, both at the end of the production process, and during the operational phase. When VLIW processors are addressed, SBST techniques can effectively exploit the parallelism intrinsic in these architectures. In this chapter, we propose a new approach that starting from existing detection-oriented programs generates a diagnosis-oriented test program. Moreover, we propose (1) a detailed analysis of the generated equivalence classes and (2) a solution aimed to maximize the diagnosability of the modules composing the VLIW processor under test, thus perfectly suiting the needs of reconfigurable systems. Experimental results gathered on a case study VLIW processor show the effectiveness of the proposed approach: at the end of the presented method, the faulty module is always identified.

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A software-based self-test and hardware reconfiguration solution for VLIW processors

Cited by 24 publications

References 12 publications

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Built-in self-repair architecture generator for digital cores

Partition-Based Faults Diagnosis of a VLIW Processor

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