A source sensing technique applied to SRAM cells

OʼConnor, Kevin

doi:10.1109/4.375972

Cited by 11 publications

(3 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Recently, several techniques have been developed to resolve the write "1" issue of the SRAM cells configured with single-ended write bit line. Some of these techniques rely on boosted word line voltage [16]- [18], reducing the supply voltage VDD [19]- [21], sizing cell transistors [22], [23], and raising the source voltage V SS [24], [25]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or may increase memory cell area.…”

Section: Proposed Technologymentioning

confidence: 99%

Two-Port SRAM Cell with Improved Write Operation

Wu¹,

Shiau²,

Yu³

et al. 2018

IJIEE

View full text Add to dashboard Cite

It is well known that in Static Random Access Memory (SRAM) cells configured with single-ended bit lines, whenever a write operation is performed, a write failure may occur. In particular, it is relatively difficult to write a logical '1' to a cell if the cell currently stores a logical '0'. It is thus necessary to provide a method of resolving write failures in memory cells. In this paper, a novel seven-transistor (7T) two-port SRAM cell incorporating an assist circuit is proposed. Wherein, the assist circuit is used to deal with the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located near to the write bit line. Accordingly, it can provide an efficient solution to the writing '1' issue to improve write operations in this manner. Simulation results for the proposed cell design confirm that there is a conspicuous improvement over the conventional two-port SRAM cells, and fast writing also can be achieved.

show abstract

Section: Proposed Technologymentioning

confidence: 99%

Two-Port SRAM Cell with Improved Write Operation

Wu¹,

Shiau²,

Yu³

et al. 2018

IJIEE

View full text Add to dashboard Cite

show abstract

“…Some of these techniques rely on boosted word line voltage [10]- [12], reducing the supply voltage VDD [8]- [9], [13]- [14], sizing cell transistors [15]- [17], reduced bit line voltage [18]- [19], and raising the source voltage V SS [20]- [22]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process.…”

Section: Existing 6t and 5t Sram Cell Topologiesmentioning

confidence: 99%

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Yu¹,

Shiau²

2017

IJIEE

View full text Add to dashboard Cite

Abstract-In this paper, a novel single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist is proposed. Amongst them, a voltage level conversion circuit is to provide a voltage of the respective connected word line to be lower than or equal to the power supply voltage VDD, as such the read/write-ability of the cell can be improved. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is design to pull up the bit line BL of a selected column to the voltage VDD before the read or write operation. Finally, with the standby start-up circuit design, the memory cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby. In particular, the paper introduce a two-phase reading mechanism to improve the reading speed, and thus to avoid unnecessary power consumption. Furthermore, by using the voltage level conversion circuit to pull the voltage of the signal WLC in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to reduce the half-selected cells disturbance.Index Terms-Read/write assist circuitry, standby start-up circuit, static random access memory, voltage level conversion circuit, voltage control circuit.

show abstract

“…In order to resolve the write '1' issue of the traditional 5T SRAM cells, several techniques have been developed. Some of these techniques rely on boosted word line voltage [10][11][12], reducing the supply voltage VDD [8][9], [13][14], sizing cell transistors [15][16][17], reduced bit line voltage [18][19], and raising the source voltage VSS [20][21][22]. However, each of these techniques may cause a reduction in the drive current of the transistors and in the operating speed of the cell, or has increased memory cell area and a degradation in the manufacturing accuracy, or requires generation of a voltage above the operating voltage, or requires a more complicated circuit design and more complicated device process.…”

Section: Existing 6t and 5t Sram Cell Topologiesmentioning

confidence: 99%

Design of High Performance Single-Port 5T SRAM Cell

Yu¹,

Shiau²

2016

IOSR

View full text Add to dashboard Cite

In this paper, a novel single-port five-transistor (5T) Static Random Access Memory (SRAM) cell and associated read/write assist is proposed. Amongst them, a word line suppression circuit is to provide a voltage of the respective connected word line to be lower than the power supply voltage V DD , as such the read/writeability of the cell can be improved and the half-selected cells disturbance can be reduced. Furthermore, a voltage control circuit is coupled to the sources corresponding to the driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. In addition, a pre-charging circuit is design to pull up the bit line BL of a selected column to the voltage V DD before the read or write operation. Finally, with the standby start-up circuit design, the memory cell can rapidly switch to the standby mode, and thereby reduce leakage current in standby.

show abstract

A source sensing technique applied to SRAM cells

Cited by 11 publications

References 20 publications

Two-Port SRAM Cell with Improved Write Operation

Two-Port SRAM Cell with Improved Write Operation

Single-Port 5T SRAM Cell with Improved Write-Ability and Reduced Standby Leakage Current

Design of High Performance Single-Port 5T SRAM Cell

Contact Info

Product

Resources

About