A stable programming pulse generator for single power supply flash memories

Tanzawa, Toru; Tanaka, Tomoharu

doi:10.1109/4.585286

Cited by 14 publications

(1 citation statement)

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“…The DCO consists of current-reference circuits and a couple of capacitor arrays. The DCO enables the clock shape to be determined only by the resistor and the capacitor, since the reference current I REF is copied to the node V CAPA and V CAPB with a current mirror [6]. The frequency and the duty cycle are robust against V DD fluctuation, global transistor V T variation and temperature variation.…”

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confidence: 99%

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD

Ishida

Yasufuku

Miyamoto

et al. 2009

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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Decreasing power consumption is the key design issue of SSDs. A typical SSD consists of more than 16 NAND Flash memories, DRAMs and a NAND controller. Since the NAND write performance is 10MB/s [1,2], to raise the write speed of SSD to the level of HDD, 100MB/s, 8 or more NAND chips in SSD are simultaneously programmed. As the feature size decreases, the total bitline capacitance in a chip increases beyond 200nF. If 8 or more NAND chips operate in parallel, a large current of 800mA flows to charge the bitline capacitance in a sub-30nm SSD [3]. A good strategy to decrease the power is lowering the supply voltage, V DD , from 3.3 to 1.8V. Yet, at 1.8V, the power consumption of conventional charge pumps, used to generate the 20V program voltage, V PGM , drastically increases and the total power consumption of the NAND does not decrease, as shown in Fig. 13.2.1(a). The charge-pump area more than doubles, which increases the NAND chip area by 5 to 10%. To overcome this problem, we implement a low-power program-voltage generator (PVG) using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller. Figure 13.2.1(b) shows our 3D-integrated SSD. NAND chips, DRAM, a NAND controller and the PVG are integrated with SiP. The PVG consists of an inductor in an interposer, the high-voltage MOS (HVMOS) and the AFD controller.An inductor is available with no area penalty by using wiring in the interposer connecting dice. The die size of the NAND decreases by 5 to 10% because no charge pump is needed. The HVMOS is fabricated with a mature NAND process and its area is just 15% of the conventional charge pump. Since the die size of the AFD controller is 0.188mm 2 with a 0.18µm CMOS process, it can be integrated in a NAND controller with a negligible area increase.A PVG using a boost converter was reported for a NOR flash memory [4]. A comparison between the PVG for a NOR flash memory and for a NAND flash memory is summarized in Fig. 13.2.2(a). In a NOR flash memory, the load of the PVG is resistive. The PVG continuously supplies a load current of 20mA at an output voltage of 5V. With a resistive load and a low output voltage, a conventional PWM is employed [4]. In a NAND flash memory, the load is capacitive and the output voltage, V PGM , is 20V. During program, V PGM is applied to the wordline and a DC load current of 20µA flows. Also, a PVG for a NAND Flash memory should support on and off modes to save power. In this condition both switching frequency and duty cycle must be dynamically optimized and the conventional PWM of changing only the duty cycle cannot be used.To identify the most power-efficient frequency and duty cycle, an input supply current, I DD , is measured with our PVG. As shown in Fig. 13.2.2(b), each V PGM has a different optimal frequency and duty cycle that minimizes I DD . In other words, the power efficiency is a function of V PGM , the switching frequency and a duty cycle, since the PVG operates in a discontinuous mode with a capacitive load. With a bit-by-bit program-verify scheme, in eac...

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