A statistical framework for post-silicon tuning through body bias clustering

Abstract

Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constraints. Assigning individual bias control to each gate leads to severe overhead, rendering the method impractical. However, assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness. In this paper, we propose a new variability-aware method that clusters gates at design time into a handful of carefully chosen independent body bias groups, which are then individually tuned post-silicon for each die. We show that this allows us to obtain near-optimal performance and power characteristics with minimal overhead. For each gate, we generate the probability distribution of its post-silicon ideal body bias voltage using an efficient sampling method. We then use these distributions and their correlations to drive a statistically-aware clustering technique. We study the physical design constraints and show how the area and wirelength overhead can be significantly limited using the proposed method. Compared to a fixed design time based dual threshold voltage assignment method, we improve leakage power by 38-71% while simultaneously reducing the standard deviation of delay by 2-9X.

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

“…If the circuit time delay is expressed as (1), the NBTI, considering the process variation, increases not only the mean time delay (d t=0 ) of the circuit, but also the standard deviation (σ total,t=0 =√Σd 2 t=0,i ) [18]. As shown in Table 1, change of the threshold voltage by T ox increased by about 2% when compared with the same change utilizing the conventional long-term model [19].…”

“…On the other hand, post-silicon tuning techniques have been introduced that allow adjustment of device characteristics after a die has been manufactured to compensate for the specific deviations that occurred due to process variations [18]. Techniques such as adaptive body biasing (ABB) and adaptive supply voltage can be used to tune the manufactured chips, thus reducing variations in circuit performance.…”

“…The body bias voltage for each individual die is different, and therefore, the body bias voltage is statistically distributed according to the probability distribution of performance. One of the postsilicon tuning methods using ABB, proposed by S. H. Kulkarni et al, clustered gates at design time into independent body bias groups, which were then individually tuned post-silicon for each die [18]. They generated the probability distribution of the post-silicon ideal body bias voltage using sampling methods for each gate.…”

Variation Tolerant AFPGA Architecture

“…Various statistical design techniques have been proposed to deal with the variation problem in CMOS design [14,15]. However, these techniques, proposed for custom VLSI and ASICs, cannot be directly applied to FPGAs in which the circuit mapping varies depending on the user design after fabrication.…”

System-level mitigation of WID leakage power variability using body-bias islands

“…More recently, in [8], the authors propose a gate-level partitioning strategy to form body-bias clusters at design time. The primary goal is to reduce the variability in leakage power dissipation using ABB, with a constraint on the clock speed of the design.…”