A stereo audio Σ∑ ADC architecture with embedded SNDR self-test

Abstract

In this paper we present a new architecture for audio Analog-to-Digital Converters (ADCs) that includes a Built-In Self-Test (BIST) technique for the test of the Signal-to-Noise and Distortion Ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sinewave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 µm CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB. IntroductionIn order to satisfy the rising demand for high quality audio devices, the performances of Sigma-Delta Analog-toDigital Converters (Σ∆ ADCs) are continuously improving with larger modulator bandwidths and higher dynamic ranges. As the performances of these circuits increase, its test is in turn more difficult and costly. Built-In Self-Test (BIST) techniques can reduce this cost by integrating the test approach in the design phase.In the last years, an intense research effort has been carried out in order to find BIST solutions for ADCs. The Oscillation-based Built-In Self-Test (OBIST) was proposed in [1] for the calculation of the input transition voltages and non-linearity errors. The main advantage of this method is that we do not need to generate an analog input stimulus for the test. However, it does not measure dynamic parameters and it takes a long test time for high-resolution converters. The oscillation-based BIST has also been applied to the test of Σ∆ modulators [2], where the modulator is reconfigured to be an oscillator. Both the frequency and the amplitude of the oscillation are measured in order to separate faulty-circuits from faultfree ones. The need to modify the circuit and the sensibility to process variations can deteriorate the quality of this BIST approach.Other authors [3,4,5,6] have proposed the estimation of the leakage in the modulator integrators, which is directly related to the quantization noise present in the bandwidth of the modulator at its output. Additionally, the same approach is used in [6] for the estimation of the settlingtime. These approaches do not allow for a complete validation of the modulator and additional tests may be necessary. Furthermore, in [3] and [4] large digital resources are required.The histogram-based technique has also been applied to the BIST of ADCs in [7]. However, only static information is obtained and long test times are necessary when the number of ...

Low-Cost Digital Detection of Parametric Faults in Cascaded $\Sigma\Delta$ Modulators

“…In particular, it is shown in [7] that the test accuracy is limited for signals close to full-scale. Similarly a fault simulation in [6] demonstrates that the proposed test underestimates the distortion in some cases. In that sense, they can help reducing the cost of a functional test flow but do not provide added value in terms of fault coverage.…”

“…In that sense, it could be compatible with the functional BIST scheme proposed in [6] that performs an SNDR test using a 1-bit digital stimulus like in [4], leading to noticeable agreement with standard SNDR test for small amplitudes. The injection of this digital stimulus relies on the same principle as for our method.…”

“…The injection of this digital stimulus relies on the same principle as for our method. As was said previously, one drawback of the approach in [6] is that it cannot detect small THD induced by near fullscale signals. Our approach would not only improve the defect coverage for this case, due to the good sensitivity to integrator settling error, but also enhance diagnosing capability.…”

“…In this way, they ensure that the quantization noise of the test stimulus remains below that of the modulator. In [6] and [7], the authors propose to use a sine-wave encoded at a higher order, so that the portion of the test stimulus quantization noise that lays in the baseband of the test stimulus is lower than that of the modulator under test. These techniques have proven useful to evaluate functional metrics at reasonable cost but with, at best, the same precision as the standard functional test they are based on.…”

Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

“…In [3], [4], [5], on-chip digital oscillators are used for generating a sinusoidal stimulus followed by ΣΔ modulation for generating a binary stream that encodes the sinusoidal stimulus. In [6], [7], [8], [9], [10], the above scheme is replaced by a Linear Feedback Shift Register (LFSR) which periodically repeats a binary sequence that encodes the sinusoidal stimulus. The binary sequence is previously selected by simulating in software an ideal ΣΔ modulator, as shown in Fig.…”