Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

Dubois, Marc-Jacques; Stratigopoulos, Haralampos-G.; Mir, Salvador

doi:10.1109/ims3tw.2012.12

Cited by 9 publications

(13 citation statements)

References 17 publications

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“…loops [17], data converters [13], DC-DC converters [4], or more general circuits [10]. The CUT can, for instance, be analyzed in the frequency domain, e.g.…”

Section: Additional Tests For Better Fault Coveragementioning

confidence: 99%

Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations

Xama

Andraud

Gomez

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

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Safety-critical and mission-critical systems, such as airplanes or (semi-)autonomous cars, are relying on an ever-increasing number of embedded integrated circuits. Consequently, there is a need for complete defect coverage during the testing of these circuits, in order to guarantee their functionality in the field. In this context, reducing the escape rate of defects during production testing is crucial, and significant progress has been made to this end. However, production testing using automatic test equipment is subject to various measurement parasitic variations, which may have a negative impact on the testing procedure and therefore limit the final defect coverage. To tackle this issue, this paper proposes an improved test flow targeting increased analog defect coverage, both at system-and block-level, by analyzing and improving the coverage of typical functional and structural tests under these measurement variations. To illustrate the flow, the technique of inserting a pseudo-random signal at available circuit nodes and applying machine learning techniques to its response is presented. A DC-DC converter, derived from an industrial product, is used as a case study to validate the flow. In short, results show that system-level tests for the converter suffer strongly from the measurement variations and are limited to just under 80% coverage, even when applying the proposed test flow. Block-level testing, on the other hand, can achieve only 70% fault coverage without improvements, but is able to consistently achieve 98% of fault coverage at a cost of at most 2% yield loss with the proposed machine-learning based boosting technique. CCS Concepts: • Computing methodologies → Neural networks; • Hardware → Design for testability; Integrated circuits; Methodologies for EDA.

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“…loops [17], data converters [13], DC-DC converters [4], or more general circuits [10]. The CUT can, for instance, be analyzed in the frequency domain, e.g.…”

Section: Additional Tests For Better Fault Coveragementioning

confidence: 99%

Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations

Xama

Andraud

Gomez

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…Digital techniques can be used to cancel harmonic components at the output of the DAC [173]. Interestingly, in the case of switched-capacitor (SC) Σ∆ ADCs, the bit stream can be fed directly into the modulator by adding simple circuitry at its input [174,175,176,177]. Another possibility is to replace the conventional sinusoidal test stimulus with a step-wise exponential [178] or, in the case of Σ∆ ADCs, with a pseudorandom pattern sequence [179].…”

Section: Data Converters Dft and Bistmentioning

confidence: 99%

Analog and Mixed-Signal Test

Stratigopoulos¹,

Kaminska²

2017

Electronic Design Automation for IC System Design, Verification, and Testing

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“…An elegant approach to overcome this issue was proposed in [17]. A sinusoidal test stimulus is encoded in a ternary stream that is composed of three logic levels {−1, 0, +1} and injected directly at the input of the modulator of the Σ∆ ADC under test.…”

Section: Previous Workmentioning

confidence: 99%

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Barragán

Alhakim

Stratigopoulos

et al. 2016

IEEE Trans. Circuits Syst. I

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This paper proposes a fully-digital BIST architecture for the dynamic test of Σ∆ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the Σ∆ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio Σ∆ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.

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Ternary Stimulus for Fully Digital Dynamic Testing of SC S? ADCs

Cited by 9 publications

References 17 publications

Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations

Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations

Analog and Mixed-Signal Test

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

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