A Strategy for Optimizing Low Operating Voltage in a Silicon Biristor

Bidenko

IEEE Electron Device Lett.

et al. 2021

Self Cite

A vertical bi-stable resistor (biristor) composed of In 0.53 Ga 0.47 As was demonstrated for sub-1 V operation. An inherent small bandgap and a scaled base length of 150 nm led to the remarkable reduction in latchup voltage compared to Si(Ge)-based conventional biristors. The epitaxially grown n-p-n structure allowed an abrupt p-n junction, which was also very important to reduce the latchup voltage. Furthermore, the physical mechanism of carrier transport in the InGaAs biristor was explored with TCAD simulations.Index Terms-3-D integration, abrupt junction artificial neural network, epitaxial growth, impact ionization, InGaAs, vertical biristor. I. INTRODUCTIONA LTHOUGH the capacitor-less one-transistor dynamic random-access memory (1T-DRAM) has shown great potential of being able to replace conventional DRAM with a higher packing density beyond 4F 2 , its three-terminal structure suffers from inherent gate reliability issues, such as hot carrier injection. [1], [2] To mitigate these issues, the bistable-resistor abbreviated as "biristor", has been developed. A biristor is an open-based two-channel bipolar junction transistor with a collector-base-emitter structure with a doping profile of either n + -p-n + or p + -n-p + . Biristors have shown promising characteristics with enhanced endurance and reliability for post-DRAM technology applications thanks to their gate-less operation. [3]-[6] Compared to 1T-DRAM, another attractive aspect of biristors is their potential for further cell size reduction thanks to their gate-less structure. In principle, when a biristor is formed vertically, the packing density can be reduced to be as small

“…As reported in previous studies [10], [11], the latch characteristics are significantly affected by the L B . Fig.…”

Section: Resultssupporting

confidence: 74%

Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

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Vertical InGaAs Biristor for Sub-1 V Operation

Bidenko

IEEE Electron Device Lett.

et al. 2021

Self Cite

“…One unit corresponds to a single cryptoristor of its own specific size. The gate length ( L G ) and channel width ( W ) were varied to find an optimal size to enable the STL ( 32 ) and sustain iterative oscillations with low power consumption. When the L G becomes long enough, the lateral electric field along the channel direction decreases, making it more difficult for impact ionization to be triggered.…”

Section: Resultsmentioning

confidence: 99%

Cryptographic transistor for true random number generator with low power consumption

Kim,

You,

Kim

et al. 2024

Sci. Adv.

Self Cite

We design a cryptographic transistor (cryptoristor)–based true random number generator (tRNG) with low power consumption and small footprint. This is the first attempt to use irregular and unpredictable operation-induced randomness of a cryptoristor as an entropy source. To extract discrete random numbers with a binary code from the cryptoristor, we developed a noise-coupling analog-to-digital converter. This converter not only converts analog signals to digital random bits but also improves the randomness of the entropy source with low power consumption. The randomness of the cryptoristor is attributed to the random carrier multiplications with the creation and stochastic carrier escape as destruction, which occurs iteratively as long as the input current is fed. The cryptoristor-based tRNG passed 15 randomness test suites of NIST Special Publication 800-22. It is robust to iterative operational stresses and to ambient temperature changes, making it an attractive option for hardware-based security solutions in the Internet of Things due to its low power consumption and small size.

“…In order to overcome these limitations, extensive research has been conducted on silicon-based highdensity memories due to their high compatibility with conventional Si CMOS processes and high-speed operations [8][9][10][11][12] . Among them, bistable resistor (biristor) and thyristor RAM (TRAM) have received much attention, with many studies being focused on their primary memory mechanisms [13][14][15][16] . The biristor memory offers signi cant advantages in achieving highly integrated arrays due to its straightforward design 8 .…”

Section: Introductionmentioning

confidence: 99%

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

Kim,

et al. 2024

Preprint

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Here, we propose a novel Schottky barrier memory (SBRAM) featuring a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.