A structure and technique for pseudorandom-based testing of sequential circuits

Muradali, F.; Nishida, Toshirou; Shimizu, Tsuguo

doi:10.1007/bf00993133

Cited by 29 publications

(14 citation statements)

References 8 publications

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“…For example, if a state variable y assumes the value 1 only rarely, then by holding a state that assigns the value 1 to y, the average frequency with which a 1 is obtained on y can be increased. A similar method was used in [6], except that in [6] all the flip-flops are controlled together, whereas in [4] the hold mode of every modified flipflop is controlled independently. The methods of [3] and [4] modify the circuit flip-flops to increase the set of reachable states, thus increasing the fault coverage that can be obtained.…”

Section: Introductionmentioning

confidence: 99%

“…A similar method was used in [6], except that in [6] all the flip-flops are controlled together, whereas in [4] the hold mode of every modified flipflop is controlled independently. The methods of [3] and [4] modify the circuit flip-flops to increase the set of reachable states, thus increasing the fault coverage that can be obtained. In this work, we are interested in maximizing the fault coverage by selecting a built-in test pattern generator for primary input sequences without modifying the circuit flip-flops.…”

Section: Introductionmentioning

confidence: 99%

“…This allows at-speed testing of the circuit under its normal operation conditions. Built-in test generation methods for synchronous sequential circuits that modify some of the circuit flip-flops were described in [3] and [4]. In [3], a subset of the flip-flops are incorporated into a partial scan or BIST register and the resulting sequential circuit is tested using weighted random patterns.…”

Section: Introductionmentioning

confidence: 99%

“…In [3], a subset of the flip-flops are incorporated into a partial scan or BIST register and the resulting sequential circuit is tested using weighted random patterns. In [4], a hold mode is added to selected flip-flops. While a flip-flop is in the hold mode, its value does not change.…”

Section: Introductionmentioning

confidence: 99%

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Built-in test generation for synchronous sequential circuits

Pomeranz

Reddy

1997

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed test application. We introduce a uniform, parametrized structure for test pattern generation. By matching the parameters of the test pattern generator to the circuit-under-test, high fault coverage is achieved. In many cases, the fault coverage is equal to the fault coverage that can be achieved by deterministic test sequences. We also investigate a method to minimize the size of the test pattern generator, and study its effectiveness alone and in conjunction with the insertion of test-points.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Built-in test generation for synchronous sequential circuits

Pomeranz

Reddy

1997

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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“…The built-in test generation methods described in [1] and [2] modify some of the circuit flip-flops, in different ways. In [1], a subset of the flip-flops are incorporated into a partial scan or BIST register and the resulting sequential circuit is tested using weighted random patterns.…”

Section: Introductionmentioning

confidence: 99%

Improved built-in test pattern generators based on comparison units for synchronous sequential circuits

Pomeranz

Reddy²

Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

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We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determination of the test sequence applied to the circuit-under-test, using fewer logic gates than the original scheme. In addition, a procedure to match the parameters of the test pattern generator to the circuit-under-test is proposed to replace the random selection used in the basic scheme. The effectiveness of these improvements is demonstrated through experimental results.

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