pseudo-random test pattern generators in BIST schemes.This new method of built-in self-test (BIST) for sequential cores on a system-on-a-chap (SOC) generates test patterns using a real-time program that runs on an embedded processor. Alternatively, the same program can be run on an external low-cost tester. This program generates patterns using circuit-specific spectral information in the f o r m of one or more Hadamard coefficients. The coefficients are extracted from high fault-coverage compacted pattern sets. W h e n an embedded processor is available on SOC, the overhead is negligible. Also, sequential cores are tested in the functional mode, avoiding activation of nonfunctional timing paths. W e present experimental results t o show that for hard to test circuits, with any given test time, spectral patterns provide signi5cantly higher fault coverage than weighted-random patterns. I IntroductionImprovements in VLSI technology in terms of gate density and increased clock speeds have made VLSI testing an integral part of chip design. Technology advances are resulting in higher operating speeds, and test equipment will fall short on keeping pace with this growing speed of circuits, thus preventing "at s p e e d test and measurement.Consequently, built-in-self-test (BIST) has emerged as a promising solution to the test problem. In addition, the recent trend of core-based system-on-a-chip (SOC) design hampers testability of embedded cores due to limited accessibility. This makes BIST the most suitable methods for testing embedded cores in the SOC environment.The main components of a BIST system are a test pattern generator that applies a sequence of patterns to the circuit under test (CUT), a response compacter that compacts the responses into a signature, and a signature comparator that compares the signature to a faultfree reference value. Due to their low hardware costs, BIST based on random patterns is very attractive. Linear feedback shift registers (LFSRs) are commonly used as

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