Novel spectral methods for built-in self-test in a system-on-a-chip environment

Abstract

pseudo-random test pattern generators in BIST schemes.This new method of built-in self-test (BIST) for sequential cores on a system-on-a-chap (SOC) generates test patterns using a real-time program that runs on an embedded processor. Alternatively, the same program can be run on an external low-cost tester. This program generates patterns using circuit-specific spectral information in the f o r m of one or more Hadamard coefficients. The coefficients are extracted from high fault-coverage compacted pattern sets. W h e n an embedded processor is available on SOC, the overhead is negligible. Also, sequential cores are tested in the functional mode, avoiding activation of nonfunctional timing paths. W e present experimental results t o show that for hard to test circuits, with any given test time, spectral patterns provide signi5cantly higher fault coverage than weighted-random patterns. I IntroductionImprovements in VLSI technology in terms of gate density and increased clock speeds have made VLSI testing an integral part of chip design. Technology advances are resulting in higher operating speeds, and test equipment will fall short on keeping pace with this growing speed of circuits, thus preventing "at s p e e d test and measurement.Consequently, built-in-self-test (BIST) has emerged as a promising solution to the test problem. In addition, the recent trend of core-based system-on-a-chip (SOC) design hampers testability of embedded cores due to limited accessibility. This makes BIST the most suitable methods for testing embedded cores in the SOC environment.The main components of a BIST system are a test pattern generator that applies a sequence of patterns to the circuit under test (CUT), a response compacter that compacts the responses into a signature, and a signature comparator that compares the signature to a faultfree reference value. Due to their low hardware costs, BIST based on random patterns is very attractive. Linear feedback shift registers (LFSRs) are commonly used as

Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns

“…The generated vectors are the same as or are very close to those generated by actual hardware and include quantization errors, which would not be included in a purely software based method [7], thus giving more pragmatic results. We implemented BIST on eight ISCAS'89 benchmark circuits.…”

“…Giani et al [7] proposed a BIST scheme that replicates beneficial spectral components using an in-built microprocessor. Chen and Hsiao [4] applied that method only to hard to detect faults.…”

“…Any bit-stream of k bits can be represented as a linear combination of Walsh functions contained in the Hadamard matrix, H(log 2 k). Hence, by spectral analysis of bit-streams supplied to primary inputs by test vectors the principal contributing Walsh functions can be determined, as described in the literature [7,19].…”

Spectral RTL Test Generation for Microprocessors

“…Hsiao and Seth [23] further expanded that work to compact testing. More recently, Giani et al [17,18] have reported spectral techniques for sequential ATPG and built-in self-test. Hsiao's group at Virginia Tech has published further work on spectrum-based self test and core test [7,8,28].…”

Spectral RTL Test Generation for Gate-Level Stuck-at Faults

“…Hsiao and Seth [12] further expanded that work to compact testing. More recently, Giani et al [9,10] have reported spectral techniques for sequential ATPG and built-in self-test. Hsiao's group at Virginia Tech has published further work on spectrum-based self test and core test [2,3,16].…”