A Study of HBM and CDM Layout Simulations Tools

Abessolo-Bidzo, Dolphin; Derikx, Richard; Cappon, Paul; Zhao, Shuang

doi:10.23919/eos/esd.2018.8509764

Cited by 3 publications

(1 citation statement)

References 7 publications

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“…Finally, it must be mentioned that transient simulation using physics-based nonlinear compact models is appropriate for IO circuit optimization, but a different or hybrid approach is required to validate the design of a full-chip protection network; see, for example, [5], [7], [84], [85]. Transient simulation with nonlinear models is too computationally expensive for full-chip verification because the netlist is very large [86].…”

Section: Discussionmentioning

confidence: 99%

Compact Models for Simulation of On-Chip ESD Protection Networks

Rosenbaum,

Huang,

Drallmeier

et al. 2024

IEEE Trans. Electron Devices

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Technology scaling and increased data rates make it near impossible to achieve historic levels of electrostatic discharge (ESD) robustness. This heightens the need for pre-Si verification that a design's ESD level is above a critical value, below which the yield loss and the number of field returns are expected to be high. Transient simulation plays a role in ESD design verification and requires the availability of accurate compact models of the various semiconductor devices, which lie along the discharge path. The compact models included in a foundry process design kit (PDK) are not accurate at ESD current levels. This article describes compact models that have been developed in the ESD device research community. It reviews the measurements used to characterize ESD protection devices and acquire data for model parameter extraction. It is concluded that obtaining accurate measurement data is challenging and this impedes the widescale adoption of ESD compact models.

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