A study of stacking limit and scaling in 3D ICs: an interconnect perspective

Abstract

An examination of large-scale stacking of 3D integrated ICs from a power-supply and thermal reliability perspective is presented. Noise characteristics and scaling issues related to through-silicon-via (TSV) size and pitch as well as other power-supply topology characteristics are included. Thermal simulations are carried out assuming the use of micro-fluidic heatsinks to provide cooling to systems with power dissipation of up to 525 watts and 46 integrated silicon tiers. Results indicate that these large systems are feasible given sufficient planning. Power-delivery-bump pitch is identified as the most important factor influencing IR-drop and dynamic noise. Contact resistance also may become a major limiting factor. I. IntroductionThe shift to the multi-core era has increased demand on the memory bandwidth of high performance processor systems. 3D integration of memory and processors has emerged as a potential solution to the memory bandwidth problem. However, there are several unanswered questions regarding 3D integration. In this work we study integration scaling from a power-supply and thermal perspective. As the number of tiers in a 3D system increase, the uppermost tiers become separated from the power supply bumps by increasing resistance and inductance. The cause of these parasitics is the through-silicon vias (TSVs) that provide communication between tiers. Additionally, increasing integration quickly raises the volumetric power density of the IC stack.The largest factor creating transient noise is the so-called "first droop" noise that results from the interaction of the inductance in the package and the on-chip decap during sleep transitions. Power gating due to sleep transitions causes large transient changes in the current demand in the power supply network. In the case of 3D systems the TSVs add inductance of their own to that which naturally exists in the package.Thermal impacts are a major factor that must be considered when designing 3D systems. For the purpose of maximum 3D integration studies standard air-cooled heatsinks will be unable to cope with the power density of these systems. Recent work has focused on implementing micro-fluidic channels [1] onto the backs of 3D stacked ICs for the purpose of removing heat using liquid-phase fluids. The heat removal capacity of these systems is very promising. In this work we assume that microfluidic heatsinks are used to dissipate heat, and design our power distribution model around this assumption.

Robust signaling techniques for through silicon via bundles

“…In 3D ICs, the variation in currents drawn in one tier can impact the supply nodes in adjacent tiers resulting in an increased dynamic noise. A significant increase in power supply noise with increase in the number of tiers is shown in [31].…”

Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability

“…Alternatively, using (ii.2) much wider ranks and presenting no I/O pins/scalability restrictions, scaling MCs in 3Dstacking is reported [9] to be limited by temperature when scaling ranks, thus restricting memory parallelism.…”

RFiof

“…Considering vertical RF-lines -as replacement of TSVs in 3D-stack systems -were employed to transfer larger width-ranks, they are likely to demand more RFpin related structures (microstrips and microstripto-coaxial interfaces), but not RFpads -replacement of I/O pads -since RFpads or equivalent are embedded and not respectively present either in RFiof or in 3Dstacking. In the latter, ranks are placed on a different 3D-layer, and when these and MCs are scaled, processor temperature is reported to be affected [11]. However, since RFiof is configured with typical ranks placed on the motherboard, ranks do not affect the processor temperature and heat dissipation.…”

“…Furthermore, although 3D-stack memories eliminate the need of I/O pins, allowing larger memory parallelism via MC scalability, researchers [11] report that rank stacking create restrictions to dissipate heat. Thus, it is fundamental to search off-chip memory solutions which are pin-and MC-scalable.…”