A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Todri, A.; Kundu, Sandip; Girard, Patrick; Bosio, Alberto; Dilillo, Luigi; Virazel, Arnaud

doi:10.1109/tvlsi.2012.2187081

Cited by 64 publications

(30 citation statements)

References 25 publications

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“…This approximation method has been adopted from [56], and it has been necessary since 3D-ICE does not support modeling TSVs. More accurate models and analysis of the analysis of the effect of copperfilled TSVs on heat transfer has been performed in [57]. Utilization of thermal vias [58], liquid microchannel cooling [59], and thermal isolation technologies [60] can improve thermal results in hot stacks.…”

Section: B Thermal Analysismentioning

confidence: 99%

A Modular Shared L2 Memory Design for 3-D Integration

Azarkhish

Rossi

Loi

et al. 2015

IEEE Trans. VLSI Syst.

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Large required size, and tolerance to latency and variations in memory access time make L2 memory a suitable option for 3-D integration. In this paper, we present a synthesizable 3-D-stackable L2 memory IP component, which can be attached to a cluster-based multicore platform through its network-on-chip interfaces offering high-bandwidth memory access with low average latency. Our design implements a scalable 3-D-nonuniform memory access (NUMA) architecture based on low latency logarithmic interconnects, which allows stacking of multiple identical memory dies (MDs), supports multiple outstanding transactions, and achieves high clock frequencies due to its highly pipelined nature. We implemented our design with STMicroelectronics CMOS-28-nm low-power technology and obtained a clock frequency of 500 MHz (limited by the access time of the memory arrays, whereas its logic components can operate up to 1 GHz), up to eight stacked dies (4 MB) with a memory density loss of 9%. Benchmark simulation results demonstrate that the addition of 3-D-NUMA to a multicluster system can lead to an average performance boost of 34%. Furthermore, experiments and estimations confirm that 3-D-NUMA is energy and power efficient (38% power reduction due to an architectural clock gating scheme), temperature friendly (over 40°C temperature reduction), and has unique features suitable for low-cost manufacturing (2.3× cost reduction due to identical MD layouts). Finally, 22% yield improvement is achievable in 3-D-NUMA compared with its 2-D counterparts, using the state of the art through-silicon-via technologies.Index Terms-3-D integration, nonuniform memory access (NUMA), physical implementation, tightly coupled data memory.

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Section: B Thermal Analysismentioning

confidence: 99%

A Modular Shared L2 Memory Design for 3-D Integration

Azarkhish

Rossi

Loi

et al. 2015

IEEE Trans. VLSI Syst.

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“…Numerical methods are based on solving a set of liner equations obtained from finite element method (FEM), finite difference method (FDM) or boundary element method (BEM). In this work, we rely on numerical methods using FDM approach based on the set of linear equations obtained from electro-thermal duality principle [6].…”

Section: Electro-thermal Analysismentioning

confidence: 99%

Fast and accurate electro-thermal analysis of three-dimensional power delivery networks

Todri‐Sanial

Bosio

Dilillo

et al. 2013

2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and

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Power delivery networks (PDNs) are essential to the optimal performance of the circuits. Reliable design of three-dimensional (3 D) PDNs faces several challenges due to parasitics of each tier PDN and Through-Silicon-Vias (TSVs). Furthermore, as 3D integration enables high circuit densities, it induces large current demand from the PDN. Because of these attributes, 3D PDNs can suffer from excessive non-uniform voltage drop and temperatures. These are further exacerbated from electro-thermal coupling, as parasitics are temperature dependent.Already 2D PDNs are challenging to analyze due to their large granularity. 3D PDNs pose additional challenge due to multi tier PDNs connected together with TSVs resulting in even larger granularities. Thus, the objective of this work is to develop fast and accurate electro-thermal models and analysis for 3D PDNs. Electro-thermal duality is exploited to develop compact electrical and thermal analytical models for 3D PDNs and TSVs. Simulation results demonstrate the accuracy of the proposed analysis method.

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“…Individual dies are aggressively thinned down and stacked on top of each other, resulting in a higher thermal resistance caused by the reduced lateral heat spreading capacity of the silicon dies and the poorly conductive adhesive materials used to bond them together. Several techniques have been proposed to address the thermal issue at different design stages, ranging from temperature-aware task allocation for multiprocessors at software level [4] to insertion of dummy thermal vias at the layout level [5]. In this scenario, reliable models which are able to capture the effects of the structures existent in 3D technology on thermal simulations play an important role to enable both early stage design decisions and accurate thermal analysis.…”

Section: Introductionmentioning

confidence: 99%

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit

Santos

Vivet

Dutoit

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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Considering the effects of thinned silicon dies and structures like TSVs and μ-bumps is essential for accurate thermal analysis of vertically integrated circuits. This paper presents an innovative compact thermal modeling approach for 3D ICs targeting system-level thermal analysis. This method uses material homogenization and formal reduction techniques for model simplification. It enables taking into account the microscopic structures required for 3D integration while keeping the model complexity affordable for fast simulations. A complete system including a packaged 65nm memory-on-logic circuit, socket and board has been modeled using the proposed thermal modeling approach. Power dissipation hot spots are emulated in the 3D circuit by using a set of resistive heaters while temperature is monitored using integrated thermal sensors. Simulation results from both steady-state and transient analyses show the thermal model is able to capture the hot spot effects with fast simulation times. Thermal data extracted from the 3D circuit demonstrate that simulation fits the thermal transient response and that steady-state analysis for various power profiles presents a worst case temperature error lower than 12% and an average error of 4.2%.

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A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Cited by 64 publications

References 25 publications

A Modular Shared L2 Memory Design for 3-D Integration

A Modular Shared L2 Memory Design for 3-D Integration

Fast and accurate electro-thermal analysis of three-dimensional power delivery networks

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit

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