A sub‐1V supply CMOS voltage reference generator

SUMMARYA novel dynamic mixed serial-parallel content addressable memory (DMSP CAM) is proposed to achieve both low-power consumption and high performance. The replica circuits provide optimal timings to enable and disable the matchline charge transistor, which maximizes performance and minimizes leakage current, respectively. The DMSP CAM does not suffer from charge sharing in the serial stage and achieves high performance by removing the predischarge or precharge operation of the matchline before every comparison. To guarantee the robustness of the proposed scheme, a statistical design methodology is also applied. Using the 45-nm technology, the DMSP CAM achieves both energy saving and performance improvement, and thus over 53% energy-delay product reduction compared with the other serial-parallel mixed CAMs.

Section: Simulation Resultsmentioning

confidence: 99%

Dynamic mixed serial–parallel content addressable memory (DMSP CAM)

Kang

Kim

Yang

et al. 2011

“…These designs are limited by the base‐emitter non‐linearities at a TC of around 20 ppm/°C, over a temperature range of 100°C. Alternative proposed topologies provide high‐order curvature compensation by cancelling part of the nonlinear dependence of the bipolar junction transistor (BJT) base‐emitter voltage, although they require complex structures with a high power consumption and large area. More recent topologies use the temperature‐dependent threshold voltage of a MOSFET and carrier mobility, to generate a PTAT voltage/current and a complementary to absolute temperature (CTAT) voltage/current, which are summed in order to provide a first‐order compensated voltage .…”

Section: Introductionmentioning

confidence: 99%

A 0.7 V, 2.7 μW, 12.9 ppm/° C over 180° C CMOS subthreshold voltage reference

Andreou

Georgiou

2016

Summary An all‐CMOS, low‐power, wide‐temperature‐range, curvature‐compensated voltage reference is presented. The proposed topology achieves a measured temperature coefficient of 12.9 ppm/°C for a wide temperature range of 180°C ( − 60 to 120°C) at a bias voltage of 0.7 V while consuming a mere 2.7 μW. The high‐order curvature compensation, which leads to a low‐temperature sensitivity of the reference voltage, is performed using a new, simple, but efficient methodology. The non‐linearities of an N‐type metal‐oxide‐semiconductor (NMOS) device operated in subthreshold are combined with the non‐linearities of two different kinds of polysilicon resistors, leading to the improved performance. The extended temperature range of this voltage reference gives it an important competitive advantage, especially at lower temperatures, where prior art designs' performance deteriorate abruptly. In addition, it utilizes an innovative trimming methodology whereby two trimmable resistors enable the tuning of both the overall slope and non‐linearities of the temperature sensitivity. The design was fabricated using TowerJazz Semiconductor's CMOS 0.18 μm technology, without using diodes or any external components such as compensating capacitors. It has an area of 0.023 mm2 and is suitable for high‐performance power‐aware applications as well as applications operating in extreme temperatures. Copyright © 2016 John Wiley & Sons, Ltd.

“…The accuracy of this method is limited by the non-linearities of the bipolar junction transistor. In order to deal with this issue, some designs utilize a curvature temperature compensation method, thus achieving improved temperature drift (TD) performance [6][7][8][9][10][11][12][13][14][15][16][17][18]. Subsequent architectures focus on using only MOS devices to generate a reference voltage [19][20][21][22][23][24][25][26].…”

Section: Introductionmentioning

confidence: 99%

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range, voltage reference

Andreou

Georgiou

2015

A low-voltage, low-power, low-area, wide-temperature-range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190°C (À60 to 130°C) while consuming only 4 μW at 0.75 V. It performs a high-order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade-off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18-μm standard CMOS technology and occupies an area of 0.039 mm 2 . The proposed reference circuit is suitable for high-precision, lowenergy-budget applications, such as mobile systems, wearable electronics, and energy harvesting systems.