A Sub-${\mu}$W/Ch Analog Front-End for $\Delta $-Neural Recording With Spike-Driven Data Compression

Kim, Seong‐Jin; Han, Su-Hyun; Cha, Ji-Hyoung; Liu, Lei; Yao, Lei; Gao, Yuan; Je, Minkyu

doi:10.1109/tbcas.2018.2880257

Cited by 41 publications

(17 citation statements)

References 41 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table I summarizes the performance of the proposed neural recording front-end and compares it with the previous works [4], [7]- [10], [13]- [15]. The silicon footprint is four times smaller than the smallest AC-coupled front-end reported, and it is comparable to the recent DC-coupled ones.…”

Section: Measurement Resultsmentioning

confidence: 95%

“…The silicon footprint is four times smaller than the smallest AC-coupled front-end reported, and it is comparable to the recent DC-coupled ones. The power consumption is the lowest [7] JSSC'15 [13] JSSC'17 [9] JSSC'18 [4] SSCL'18 [14] JSSC'18 [8] TBCAS'19 [15] TBCAS'20 [10] This work 2 On-chip decimation filter. 3 Off-chip decimation filter.…”

Section: Measurement Resultsmentioning

confidence: 99%

See 1 more Smart Citation

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

Uran

Leblebici

Emami

et al. 2020

IEEE Solid-State Circuits Lett.

View full text Add to dashboard Cite

This paper presents an energy-and-area-efficient ACcoupled front-end for multichannel recording of wideband neural signals.The proposed unit conditions local field and action potentials using an inverter-based capacitively-coupled low-noise amplifier, followed by a perchannel 10-bit asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65nm CMOS achieves 4× smaller area and 3× higher energy-area efficiency compared to the state of the art with 164 µm×40 µm footprint and 0.78 mm 2 ×fJ/conv-step energy-area figure of merit. The measured 0.65 µW power consumption and 3.1 µVrms input-referred noise within 1Hz-10kHz bandwidth correspond to a noise efficiency factor of 0.97. Index Terms-AC coupling, front-end, inverter-based amplifier, monotonic switching, neural recording, successive approximation register analog-to-digital-converter, unit length capacitor.

show abstract

Section: Measurement Resultsmentioning

confidence: 95%

Section: Measurement Resultsmentioning

confidence: 99%

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

Uran

Leblebici

Emami

et al. 2020

IEEE Solid-State Circuits Lett.

View full text Add to dashboard Cite

show abstract

“…Although numerous neural recording headstages have been already developed and optimized for their specific application domain (e.g., for very large scale arrays [12][13][14][15] , or for intracranial recordings 38,[52][53][54][55][56][57], to our knowledge, this is the first instance of a headstage design that has the capability of adapting to numerous use cases requiring different gain factors and band selections, on the same input channel.…”

Section: Discussionmentioning

confidence: 99%

An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

Sharifhazileh

Burelo

Sarnthein³

et al. 2020

Preprint

View full text Add to dashboard Cite

The analysis of biomedical signals for clinical studies and therapeutic applications can benefit from compact and portable devices that can process these signals locally, in real-time, without the need for off-line processing. An example is the recording of intracranial EEG(iEEG) during epilepsy surgery with the detection of High Frequency Oscillations (HFOs, 80-500 Hz), which are a biomarker for the epileptogenic zone. Conventional approaches of HFO detection involve the offline analysis of prerecorded data, often on bulky computers. However, clinical applications during surgery or in long-term intracranial recordings demand a self-sufficient embedded device that is battery-powered to avoid interfering with other electronic equipment in the operation room. Mixed-signal and analog-digital neuromorphic circuits offer the possibility of building compact, embedded, and low-power neural network processing systems that can analyze data on-line and produce results with short latency in real-time. These characteristics are well suited for clinical applications that involve the processing of biomedical signals at (or very close to) the sensor level. In this work, we present a neuromorphic system that combines for the first time a neural recording headstage with a signal-to-spike conversion circuit and a multi-core spiking neural network (SNN) architecture on the same die for recording, processing, and detecting clinically relevant HFOs in iEEG from epilepsy patients. The device was fabricated using a standard 0.18μm CMOS technology node and has a total area of 99 mm2. We demonstrate its application to HFO detection in the iEEG recorded from 9 patients with temporal lobe epilepsy who subsequently underwent epilepsy surgery. The total average power consumption of the chip during the detection task was 614.3 μW. We show how the neuromorphic system can reliably detect HFOs: the system predicts postsurgical seizure outcome with state-of-the-art accuracy, specificity, and sensitivity (78%, 100%, and 33% respectively). This is the first feasibility study towards identifying relevant features in intracranial human data in real-time, on-chip, using event-based processors and spiking neural networks. By providing “neuromorphic intelligence” to neural recording circuits the approach proposed will pave the way for the development of systems that can detect HFO areas directly in the operation room and improve the seizure outcome of epilepsy surgery.

show abstract

“…Different researchers have focused on different features in their design. For example, some studies have focused on the low power of the amplifier [11,12], some have pursued low noise [13,14,15], while others have paid more attention to the NEF [16,17,18,19], high input impedance [20,21], little distortion [22,23,24] and small area [25,26]. A tradeoff exists between power, noise and area and balancing these performances in design is important.…”

Section: Discussionmentioning

confidence: 99%

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Ni¹,

Han²,

Lei³

et al. 2020

Preprint

View full text Add to dashboard Cite

Background: Recording of electrical activity of neurons is indispensable for decoding the information in the brain. The amplitude of signals recorded by electrodes is small, and it must be amplified to the level that can be digitalized by the analog-to-digital convert (ADC). A micro-power low-noise neural recording amplifier is indispensable for implant hippocampal cognitive prosthesis. When the process turns into deep submicron, the gate leakage current of the metal oxide semiconductor (MOS) transistor becomes larger and mismatch between devices becomes worsen. It is necessary to keep the neural amplifier robust in all process corners. Methods: The proposed circuit is a two-stage amplifier which can achieve a good trade-off between power consumption and noise. Four second-stage amplifiers share a common reference amplifier to reduce area and power consumption. A pseudo-resistor with high resistance is utilized to realize a very-low frequency high pass corner without external components. In order to minimize process variation, a bulk-compensated (BC) technique is adopted to maintain adequate tolerance in all corner case. Results: The 4-channel neural amplifier is designed and fabricated in a 40 nm standard complementary metal oxide semiconductor (CMOS) process. It achieves a mid-band gain of 54 dB, a bandwidth of 70 Hz to 7.7 kHz, a total input-referred noise of 3.2 μVrms , and a Noise Efficiency Factor (NEF) of 3.3 while consuming 4.68 µW from the 1.1 V supply. The core area of one channel is only 0.032 mm 2 . Conclusion: A 4-channel integrated neural recording amplifier chip with bias-compensated circuits is presented in this paper. Extensive simulations insure that the design is “center”. The chip layout is verified using design rules check (DRC) and layout versus schematic (LVS) design check with the help of verification tools. Test results shows that it is less sensitive to process variation and consumes less power compared with amplifier without bulk-compensated circuit. This makes the design robust and uniquely appropriate for low-power implant application.

show abstract

A Sub-${\mu}$W/Ch Analog Front-End for $\Delta $-Neural Recording With Spike-Driven Data Compression

Cited by 41 publications

References 41 publications

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Contact Info

Product

Resources

About

A Sub-${\mu}$W/Ch Analog Front-End for $\Delta $-Neural Recording With Spike-Driven Data Compression

Cited by 41 publications

References 41 publications

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

An electronic neuromorphic system for real-time detection of High Frequency Oscillations (HFOs) in intracranial EEG

A Robust 4-channel Micro-power Low-noise Neural Recording Amplifier for Hippocampal Cognitive Prosthesis

Contact Info

Product

Resources

About

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm²×fJ/conv-step Efficiency and 0.97 NEF