A sub-V<inf>T</inf> 2T gain-cell memory for biomedical applications

Abstract

Abstract-Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, lowleakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 10 4 times higher than the access time. Monte Carlos simulations show that the 2 kb gaincell array, implemented in a mature 0.18 µm CMOS node and supplied with a sub-VT voltage of 400 mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

“…Therefore, an accurate estimation of DRT is required to achieve low power operation. Various metrics have been used for simulating the DRT of a bitcell [3], [5], [6], but the unequivocal definition of this important parameter is the time at which the voltage written to C SN degrades to the point where it results in an incorrect readout. This time is set by four primary factors: the initial level stored on C SN following a write, the size of C SN , the leakage currents to and from SN, and the readout mechanism.…”

Review and classification of gain cell eDRAM implementations

“…The positive impact of supply voltage scaling on retention time for given access statistics and a given write bitline control scheme is demonstrated in [18], proposing near-threshold (NVT) operation for longer retention times and therefore lower retention power. A recent study [19] shows that the supply voltage of GC arrays can even be scaled down to the subthreshold (sub-V T ) domain, while still guaranteeing robust operation and high memory availibility for read and write operations. E. Comparison of State-of-the-Art Implementations Fig.…”

“…The common feature for all these circuits is their reduced device count, as compared to traditional SRAM circuits. The highest device count appears in [13], comprising three transistors and a gated diode, with all other proposals made up of two [3,5,11,15,18,19,22] or three [2,[8][9][10]12,14,20,21,24] transistors. The obvious implication of the transistor count is the bitcell size; however, the choice of the topology is application dependent, as well.…”

“…A few recent publications design and optimize GC memories for use in wireless communications systems or other fault-tolerant systems, while other work has verified the feasibility of lowvoltage operation, making GC arrays good candidates for biomedical systems. [2,3,5,[8][9][10][11][12][13][14][15][16][17][18][19][20][21].…”

“…The reduced device count results in a much higher bitcell density, as compared to a standard SRAM, while the decoupled read port provides both a non-destructive read operation and two-ported functionality. Neither read nor write operations suffer from the ratioed contention between devices in a 6T SRAM, resulting in increased margins and enabling voltage scaling [15,19]. Finally, leakage power is highly reduced, as fewer devices suffer from Drain Induced Barrier Lowering (DIBL), and scaled supply voltages reduce other leakage components.…”