Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Teman, Adam; Meinerzhagen, Pascal; Giterman, Robert; Fish, Alexander; Burg, Andreas

doi:10.1109/tcsii.2014.2305016

Cited by 24 publications

(16 citation statements)

References 9 publications

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“…When a “1” data in BL_W is written to a row selected cell, the “0” storages of unselected bit‐cells in the same BL_W are upset significantly by the subthreshold current as depicted in Figure A. This write “1” disturbance is fatal to the retention of all‐PMOS gain cells . In our design, the common C_BD in an 8‐kbit sub‐array is boosted to V BB during the write access; hence, the subthreshold leakages in the unselected “0” cells are lowered intensively because of the negative source‐to‐body bias.…”

Section: Memory Structure and Operationmentioning

confidence: 98%

P‐channel logic 2 T eDRAM macro with high retention bit architecture

Manisankar

Chung

2018

Circuit Theory & Apps

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Summary This study presents a novel approach which enhances the data retention capability of PMOS gain cell based embedded DRAM. The proposed circuit technique utilizes a parasitic capacitance between the cell storage node and the common n‐well body. During the write operation, an up‐down voltage transition to the n‐well increases the cell storage retention time without using any optional devices. It also results in much high immunity against the write “1” disturbance. Measured and simulated results from an 8192‐wordx8‐bit eDRAM macro implemented in a 0.13‐μm generic CMOS process exhibit 58% increased retention time and approximately 3.6 times stronger write disturbance immunity over the conventional design.

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Section: Memory Structure and Operationmentioning

confidence: 98%

P‐channel logic 2 T eDRAM macro with high retention bit architecture

Manisankar

Chung

2018

Circuit Theory & Apps

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“…The increased aggregated sub-V T current causes faster degradation of the stored charge, leading to reduced DRT, as compared to a reference 2T cell. In addition, several previous works have shown that the data dependent, asymmetric DRT (for data '0' and '1') of standard GCs can be manipulated to overall enhance DRTs by biasing the WBL at the best-case voltage for the weaker data level during standby and read operations [10]. For the proposed 3T configuration, the worst-case DRTs of the '1' and '0' levels are similar, and significant deterioration of the stored levels occurs for both extreme values of WBL bias (V DD and GND).…”

Section: B Write Circuitrymentioning

confidence: 99%

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Giterman

Teman

Meinerzhagen

et al. 2016

IEEE Trans. VLSI Syst.

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Abstract-Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as non-trivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single supply voltage and provides superior write capability to conventional GC structures. The proposed circuit is demonstrated with a 2 kb memory macro that was designed and fabricated in a mature 0.18 µm CMOS process, targeted at low-power, energyefficient applications. The test array is powered with a single supply of 900 mV, showing an 0.8 ms worst-case retention time, a 1.3 ns write-access time, and 2.4 pW/bit of retention power. The proposed topology provides a bitcell area reduction of 43%, as compared to a redrawn 6T SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

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“…As shown in figure 3, the worst-case distance between two consecutive read accesses is no more than a few thousand cycles which is very much within the retention time and speed-assurance period of the 3T1D cell. It should be noted that the eDRAM cell used in this proposal is logic compatible meaning it can be integrated on-chip without extra manufacturing process steps and several previous studies have discussed in detail the feasibility of a L1 cache design using such eDRAM cells [18], [19].…”

Section: Table II Xor Logic During Read For Inverting Input/output Bamentioning

confidence: 99%

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

Ganapathy

Canal

González

et al. 2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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Abstract-Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical variations of process parameters, it can potentially render systems dysfunctional in certain scenarios. Data caches suffer the most from such phenomenon because of the unbalanced duty cycle ratio of SRAM cells and maximum intrinsic susceptibility to process variations. In this paper, we propose a novel NBTI-aware technique, invertRead-Modify-Write (iRMW) that can improve the functional yield of the data cache significantly over its lifetime. Using architecture-level benchmarks, we first analyse the impact of activity factor and workload variation on NBTI-induced failures in data caches. iRMW is then used as a means to balance the duty cycle by alternating between recovery and stress cycle upon successive read accesses to the cache line. The highly transient nature of the data stored in L1 data cache aides this process of recovery upon using iRMW. A unique feature of iRMW is its intelligent use of low-leakage & NBTI-tolerant embedded-DRAM cells as an alternative to SRAM-cells for storing important state information. Our experiments conducted using SPEC2006 and PhysicsBench workloads show that on-average the cache failure probability can be reduced by 22%, 33% and 36% after two, four and eight years of processor usage respectively. In addition to being extremely power-frugal, use of eDRAM reduces total area footprint of iRMW tremendously.

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Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Cited by 24 publications

References 9 publications

P‐channel logic 2 T eDRAM macro with high retention bit architecture

P‐channel logic 2 T eDRAM macro with high retention bit architecture

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

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