Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

Abstract

Abstract-Logic compatible gain cell (GC) embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, non-ratioed operation, low static leakage, and 2-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as non-trivial level shifting and toleration of high voltage levels. In this paper, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single supply voltage and provides superior write capability to conventional GC structures. The proposed circuit is demonstrated with a 2 kb memory macro that was designed and fabricated in a mature 0.18 µm CMOS process, targeted at low-power, energyefficient applications. The test array is powered with a single supply of 900 mV, showing an 0.8 ms worst-case retention time, a 1.3 ns write-access time, and 2.4 pW/bit of retention power. The proposed topology provides a bitcell area reduction of 43%, as compared to a redrawn 6T SRAM in the same technology, and an overall macro area reduction of 67% including peripherals.

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

“…The DRT is defined as the time after write, at which the stored data can no longer be correctly read out, and consequently, the refreshrate must be set to ensure that the data is rewritten before the DRT has passed. While the average DRT of the array is sufficiently high, the DRT distribution has a wide spread across several orders-of-magnitude, primarily due to random dopant fluctuations (RDF), which significantly affect the V T of NW [7], [10]. In order to ensure that no DRT errors occur, the refresh-rate is usually set according to the cell with the worst data retention, as extracted from high-sigma analysis under the assumption of worst-case operation.…”

“…However, the dynamic nature of gain-cells requires the application of The associate editor coordinating the review of this manuscript and approving it for publication was Tae Hyoung Kim. periodic refresh operations to maintain the data, which is stored on a parasitic MOSFET gate capacitor. While gain-cell implementations in mature technology nodes were shown to provide sufficiently high data retention times (DRTs) [6], [7], gain-cell embedded DRAM (GC-eDRAM) implementations in 65 nm nodes and below demonstrate significantly lower DRTs due to increased leakage currents and decreased parasitic storage capacitances [8], [9]. Furthermore, the refreshrate of GC-eDRAM is commonly set according to the worst DRT of all cells in a memory array, simulated under worst-case biasing conditions and PVT variations [6]- [9].…”

Modem Gain-Cell Memories in Advanced Technologies

“…The time in between refreshes is defined as retention time. ST [3] IBM [4] Reneseas/Ko [9] EPFL [10] UM/LDPC [11] Hitachi [12] STARC [13] Intel/Memory [14] UM/Biomedical [15] EPFL/Biomedical [16] Samsung/Camera [17] Industrial Products…”

P‐channel logic 2 T eDRAM macro with high retention bit architecture

“…Fundamentally, a unit gain cell is built with 2-MOSFET (2 T) and optional devices such as a gated diode, a MOSFET capacitor, or additional MOSFETs. The gain memory cells with optional devices [2][3][4][5][6][7] can enhance the bit retention time; however, they consume a spacious unit-cell area. The 2 T structure in mixed type of an n-channel MOSFET and a pchannel MOSFET 8 also carries considerable bit-area penalty due to the large well-to-well space.…”