ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) 2001
DOI: 10.1109/icecs.2001.957609
|View full text |Cite
|
Sign up to set email alerts
|

A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 /spl mu/m CMOS using self calibration and low power techniques

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
6
0

Year Published

2006
2006
2013
2013

Publication Types

Select...
3
3

Relationship

0
6

Authors

Journals

citations
Cited by 7 publications
(6 citation statements)
references
References 5 publications
0
6
0
Order By: Relevance
“…[31] [18][35] [11] Fig. 19 The ADCs in Table 2 are ranked according to the power dissipation and sorted, from which ten best have been shown Analog Integr Circ Sig Process (2011) 66:389-405 403 fabricate micro structures in a smaller dimensions, which makes parasitic capacitive load smaller, and in this way reduces the power dissipation.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…[31] [18][35] [11] Fig. 19 The ADCs in Table 2 are ranked according to the power dissipation and sorted, from which ten best have been shown Analog Integr Circ Sig Process (2011) 66:389-405 403 fabricate micro structures in a smaller dimensions, which makes parasitic capacitive load smaller, and in this way reduces the power dissipation.…”
Section: Discussionmentioning
confidence: 99%
“…The ranking of ADCs based on the use of capacitive DAC is difficult and gives a distorted picture of its useability because this subject have never been studies from the low frequency perspective and even in the publicly accepted definition of the figure of merit the high operation speed is a merit [10]. Reason, why the capacitive DAC was not used in this research was that no area efficient capacitor was available at the time by the IC fabricator [11][12][13][14][15][16][17].…”
mentioning
confidence: 84%
“…The basic structure of 16-channels 10bit 1MHZ SAR ADC as shown in Figure 2, consists of 16 analog sampling switches, sample and hold circuit, analog-to-digital converter (DAC), comparator, successive approximation logic register and the timing control circuit [1][2][3][4][5]. The principle of SAR ADC is using the binary search algorithm that makes the output of the DAC successively approximate input signal.…”
Section: Sar Adc Designmentioning
confidence: 99%
“…These applications do not require high speed or high resolution converters, but low power is mandatory. Nevertheless this type of converter is also use in high resolution applications [4][5] .…”
Section: Introductionmentioning
confidence: 99%
“…Some low-power converters, such as [6], [2] and [3] work at sampling frequencies of MS/s with resolutions between 5 and 6 bits and power consumption between 3 and 30 mW. Reference [4] presented a 16 bits resolution low-power converter working at kS/s with power consumption around 7mW. An ultra-low-power consumption converter as the presented in [1] can achieve 16b resolution working at 200 Hz with a consumption of 22.2 piW.…”
Section: Introductionmentioning
confidence: 99%