A survey of digital design reuse

Abstract

As integrated circuit technologies advance toward higher performance, greater densities, and increasing system complexity, CAD tools and design methodologies struggle to keep pace. Managing the formidable complexity of the design process is one of the main challenges to IC design. Disseminating design reuse is central to bringing the design effort's complexity back to a manageable size. Effective reuse, though, takes more than just gathering predesigned components in a library. Reuse-oriented policies and strategies must permeate the entire design process, from the methodologies themselves to the final designs.In this article, we provide a brief overview of the state of the art in design reuse for digital systems. We also discuss the challenges posed to this discipline by the recent trend toward integrating processor cores in high-volume application-specific integrated circuits.Design reuse, particularly in the core-based system-on-chip (SOC) design era, is no longer a discipline in isolation. Reuse cannot be fully separated from simulation and verification, estimation, synthesis, or test. For example, the "Design Section" of the 1999 edition of the International Technology Roadmap for Semiconductors emphasized the need for synthesis technology to support the reuse of predesigned General-purpose VHDL-based reuse Preis et al. proposed a domain-independent, VHDL-based reuse methodology for a hypertextbased reuse environment. 2 At the core of this A Survey of Digital Design Reuse Design Reuse 98 The authors survey recent advances in digital design reuse. They stress the need for effective strategies that accommodate reuse throughout the entire design process.

Soft IP Compiler for a Reed-Solomon Decoder

“…When an IP user selects the exact parameter set within the system requirement, the generation process merely instantiates the target model as modifying statements, such as "generic" and "constant" in VHDL, from the baseline design. Increasing functionality and reusability of a parameterized soft macro, however, especially extending the parameter set in the IP core, often makes it difficult for design refinements to meet design constraints managed by a checklist [3]. Since system designers may not know the precise characteristics of an IP block that they place into a silicon wafer, when a parameterized IP has extended parameters for more flexibility, it is never an easy problem to search for an optimal parameter set within the design space.…”

Active control and digital rights management of integrated circuit IP cores

“…Methods for digital design reuse and intellectual property trading are emerging [2,22,14,5,7,6]. Protection of IPs in the reuse-based design flow is of paramount importance, but the prior work on individual IP protection has been limited.…”

“…Because of the complexity, adapting the design reuse paradigm is the key to address constraints such as lowpower, real-time budgets, silicon efficiency, time-to-market, and low cost [14]. A consequence of the current shift towards the fabless business model and design reuse is increased horizontalization of the microelectronic industry.…”

Embedded architecture description language

“…This makes component-based development (CBD), developing systems via assembly of components, an appealing and appropriate approach to embedded system development. In both hardware and software industries, CBD [6,15] is a common trend. (In hardware industry, CBD is also known as Intellectual Property (IP) based development.)…”