A survey of research and practices of Network-on-chip

Abstract

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

Customizing Reconfigurable On-Chip Crossbar Scheduler

“…The functionality of the network is verified by VHDL simulations. From the implementation, k 1 = k 2 = k 3 = 1 have been obtained for Equation (3). The crossbar network with our scheduler has been implemented with the following specific steps.…”

“…In this paper, we present a custom crossbar scheduler utilizing on-demand reconfigurable interconnects. Numerous NoCs targeting ASICs (surveyed in [3]) employ rigid underlying physical networks. Typically, packet routers constitute tiled NoC architectures and each packet router accommodates a crossbar switch fabric and a scheduler for internally all-to-all physical interconnects.…”

“…A request is served after a request in the previous port index is arbitrated and/or the link is established. Subsequently, 24 cycles are required in total, as depicted in Figure 2 (3). Figure 2(4) depicts our implemented FPS, where homogeneous arbiters are located in each port.…”

“…This is mainly because the topology of interconnects inside the scheduler module is all-to-all. The crossbar scheduler is also an important basic building block for modern networks-on-chip (NoC) [3]. The scheduler in the on-chip router also accommodates all-to-all connections.…”

A Hardware-Software Design Framework for Distributed Cellular Computing

“…One of the main challenges in today's hardware architectures resides in implementing versatile communication capabilities that are able to provide a sufficient bandwidth whilst remaining cost-and size-efficient, as evidenced in research on Network-On-Chip [2] and other systems [8]. This aspect of parallel systems is unfortunately often ignored in bio-inspired hardware approaches and is another of the factors that prevent the implementation of complex applications.…”