A Survey on Low-Power Techniques for Single and Multicore Systems

Zandrahimi, Mahroo; Al-Ars, Zaid

doi:10.4108/icst.iccasa.2014.257372

Cited by 2 publications

(3 citation statements)

References 31 publications

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“…The total current discharging in the footer transistor is given by (8). The variable αswitching is the percentage of switching gates in the corresponding cluster, N is the number of the total gates in the cluster, and IGates is the discharging current of a single gate.…”

Section: Footer Transistor Sizingmentioning

confidence: 99%

A Review on Random Dopant Fluctuation Impact on Within-Die Variation

Sreeja¹,

Athira²,

Dhanya³

et al. 2017

IJERT

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Process variation creates core-speed discrepancy among the core in many-core platforms. Random variation is one of the important components that contribute into core-speed discrepancy. In the paper, a novel technique is proposed that uses footer transistors to reduce the delay and power in a manycore platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the randomdopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor minimizing the static power dissipation.

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Section: Footer Transistor Sizingmentioning

confidence: 99%

A Review on Random Dopant Fluctuation Impact on Within-Die Variation

Sreeja¹,

Athira²,

Dhanya³

et al. 2017

IJERT

View full text Add to dashboard Cite

show abstract

“…Power is one of the primary design constraints and performance limiters in the semiconductor industry. Reducing power consumption can extend battery life-time of portable systems, decrease cooling costs, as well as increase system reliability [19]. Various low power approaches have been implemented in the IC manufacturing industry, among which adaptive voltage scaling (AVS) has proven to be a highly effective method of achieving low power consumption while meeting the performance requirements.…”

Section: Introductionmentioning

confidence: 99%

“…AVS is also used to enhance yield; operating voltage of fast chips is reduced to compensate for extra leakage power, while operating voltage of slow chips is increased to reach the performance target. In addition, AVS can be used to improve power efficiency per die by reducing the voltage supply to the optimum voltage at the transistor level [19].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

et al. 2019

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With the continued down-scaling of IC technology and increase in manufacturing process variations, it is becoming ever more difficult to accurately estimate circuit performance of manufactured devices. This poses significant challenges on the effective application of adaptive voltage scaling (AVS) which is widely used as the most important power optimization method in modern devices. Process variations specifically limit the capabilities of Process Monitoring Boxes (PMBs), which represent the current industrial state-of-the-art AVS approach. To overcome this limitation, in this paper we propose an alternative solution using delay testing, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS'99 benchmarks with 28nm FD-SOI library, that using delay test patterns result in an error of 5.33% for transition fault testing (TF), error of 3.96% for small delay defect testing (SDD), and an error as low as 1.85% using path delay testing (PDLY). In addition, the paper also shows the impact of technology scaling on the accuracy of delay testing for performance estimation during production. The results show that the 65nm technology node exhibits the same trends identified for the 28nm technology node, namely that PDLY is the most accurate, while, TF is the least accurate performance estimator.

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A Survey on Low-Power Techniques for Single and Multicore Systems

Cited by 2 publications

References 31 publications

A Review on Random Dopant Fluctuation Impact on Within-Die Variation

A Review on Random Dopant Fluctuation Impact on Within-Die Variation

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

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