A systematic study of trade-offs in engineering a locally strained pMOSFET

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.Index Terms-MOSFET, SiGe, strained-silicon, technology computer-aided design (TCAD).

Section: Introductionmentioning

confidence: 99%

Exploring the limits of stress-enhanced hole mobility

Smith

Moroz

Eneman

et al. 2005

“…The bulk-Si piezoresistance (PR) coefficients [12] have been found to predict mobility enhancements with good accuracy for bulk-Si MOSFETs [4], [13] as well as MuGFETs [8]. summarizes the expected percentage change (calculated from the PR coefficients) in electron (NMOS) and hole (PMOS) mobilities per 1-GPa tensile stress in each axis direction.…”

Section: Resultsmentioning

confidence: 99%

Study of bending-induced strain effects on MuGFET performance

Shin

Xiong

Cho

et al. 2006

The impact of stress induced by biaxial mechanical bending on multiple-gate FET (MuGFET) performance is studied. For relatively low levels of bending-induced surface strain (∼ 0.1%), significant enhancements in the driving current can be achieved and maintained with gate-length scaling. This makes package strain a potentially attractive approach to enhancing MuGFET-based CMOS performance at low cost. For bending-induced strain, the enhancements in electron mobility and (110) hole mobility are well predicted by the piezoresistance model using the coefficients for bulk-Si, but the impact of stress on (100) hole mobility is more complex.

“…Each individual stressor gives approximately 21% enhancement while the combination results in a 55% increase in I dsat at a constant I off of 100 nA/µm. Using an optimized Si 0.8 Ge 0.2 process as described in [3] and [4], the combination of Si 0.8 Ge 0.2 and c-CESL results in an 85% increase in I dsat for a 70-nm-gate length. Even though the process was not yet optimized for smaller gate lengths, this saturation current enhancement at fixed OFF-state current was still maintained at a polylength of 45 nm (Fig.…”

Section: Device Fabrication and Electrical Resultsmentioning

confidence: 99%

pMOSFET with 200% mobility enhancement induced by multiple stressors

Washington

Nouri

Thirupapuliyur

et al. 2006

Recessed Si 0.8 Ge 0.2 source/drain (S/D) and a compressive contact etch-stop layer have been successfully integrated resulting in nearly 200% improvement in hole mobility. This is the largest reported process-induced hole mobility enhancement to the authors' knowledge. This letter demonstrates that a drivecurrent improvement from recessed Si 0.8 Ge 0.2 plus the compressive nitride layer are in fact additive. Furthermore, it shows that the mobility enhancement is a superlinear function of stress, leading to larger than additive gains in the drive current when combining several stress sources.Index Terms-MOSFET, SiGe, strained-silicon, technology computer-aided design (TCAD).