A ternary memory cell using small Josephson junction arrays

Nair, Niketh; Braiman, Yehuda

doi:10.1088/1361-6668/aae2a9

Cited by 9 publications

(5 citation statements)

References 36 publications

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“….15 mA −0.17 mA −0.12 mA operation for DC bias current values. The experiments also verify the principle upon which similarly designed ternary[34] or higher order cells could operate. These cells do not require alternative Josephson junction designs, or novel fabrication techniques.…”

mentioning

confidence: 53%

“…From the figure it is also clear that, given appropriate inductance values and bias currents, there can be more than two possible fixed-point states (e.g. the three-state system in [34]). We summarize the fixed-point solutions of the four circuits designed for this test in table 2.…”

Section: Imentioning

confidence: 99%

“…We would like to emphasize that memory cell states in our design, in principle, are not characterized by the presence and/or absence of fluxons; a variety of different memory states could be attributed to the same number of fluxons stored in the circuit. The response of the memory cell circuit to the applied SFQ pulse (for read, write, or reset operations) could be digital (meaning the outcome is certain amount of flux quanta) or analog (meaning the output are voltage pulses that are less than an SFQ, as in the NDRO proposed in [34]). In the specific instance used for this paper, the two states differ by a fluxon, however this is not necessary for other cells based on the paradigm used for this one.…”

Section: Imentioning

confidence: 99%

“…Moreover, multivalued memory cells based on the proposed memory cell can be considered. Recently we have presented a ternary memory cell [34] that consists of the same circuit topology (three inductively coupled Josephson junctions) and same operating principles as the recently introduced binary memory cell [30].…”

Section: Introductionmentioning

confidence: 99%

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Experimental demonstration of a Josephson cryogenic memory cell based on coupled Josephson junction arrays

Nair

Jafari-Salim

D’Addario

et al. 2019

Supercond. Sci. Technol.

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In this paper, experimental verification for a cryogenic memory cell consisting of three inductively coupled Josephson junctions is presented. Design and operational logic of this type of cell was recently introduced. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and this type of memory cell is fundamentally different from the existing single flux quantum-based memory cells. Here, we present design principles and experimental validation for write operations and readout operation for four versions of the design, each with different parameters. Our experimental results show excellent resemblance with the previously presented memory cell operational logic and also show an excellent fit with simulations of the entire memory cell circuit that includes the memory cell and all the peripheral circuitry.

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mentioning

confidence: 53%

Section: Imentioning

confidence: 99%

Section: Imentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Experimental demonstration of a Josephson cryogenic memory cell based on coupled Josephson junction arrays

Nair

Jafari-Salim

D’Addario

et al. 2019

Supercond. Sci. Technol.

Self Cite

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“…This multilevel operation is significantly different from previously reported superconducting nanowirebased memories, which have thus far been predominantly binary devices 16 26 27 . It has recently been argued that multilevel memory may compensate for the large power consumption of peripheral circuits in superconducting memory arrays by providing a higher information capacity per cell given the same peripheral circuitry; additionally, multilevel memories may allow for increased memory density as the limits of physically shrinking a memory unit are reached 28 . Thus, future investigation of the device presented here as a multilevel memory may advance the scaling of superconducting memory arrays.…”

Section: Discussion On Applicationsmentioning

confidence: 99%

Bridging the Gap Between Nanowires and Josephson Junctions: A Superconducting Device Based on Controlled Fluxon Transfer

et al. 2019

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The basis for superconducting electronics can broadly be divided between two technologies: the Josephson junction and the superconducting nanowire. While the Josephson junction (JJ) remains the dominant technology due to its high speed and low power dissipation, recently proposed nanowire devices offer improvements such as gain, high fanout, and compatibility with CMOS circuits. Despite these benefits, nanowire-based electronics have largely been limited to binary operations, with devices switching between the superconducting state and a high-impedance resistive state dominated by uncontrolled hotspot dynamics. Unlike the JJ, they cannot increment an output through successive switching, and their operation speeds are limited by their slow thermal reset times. Thus, there is a need for an intermediate device with the interfacing capabilities of a nanowire but a faster, moderated response allowing for modulation of the output. Here, we present a nanowire device based on controlled fluxon transport. We show that the device is capable of responding proportionally to the strength of its input, unlike other nanowire technologies. The device can be operated to produce a multilevel output with distinguishable states, which can be tuned by circuit parameters. Agreement between experimental results and electrothermal circuit simulations demonstrates that the device is classical and may be readily engineered for applications including use as a multilevel memory.

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