A ternary memristor full adder based on literal operation and module operation

Abstract

A ternary memristor full adder is designed based on the literal operation and module‐3 plus operation. Literal operation and module‐3 plus operation are the important operations in the tri‐valued algebra system. Multiple‐valued logic can increase the amount of information carried by the signals and reduce the number of devices and connections. The combination of multiple‐valued logic and memristor is an exploration of new devices and new structures. The novel ternary memristor full adder owns the advantage of simpler structure without decoding units to convert ternary signals to binary at the terminals, and all the signals operated by the circuit are ternary. Compared with the traditional ternary full adder, the number of devices and the power consumption are greatly reduced. Simulation results of different memristor models verified the correctness and applicability of the circuit design. It provides a new idea for the design method of memristor circuits, especially multiple‐valued memristors.

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

“…This popularity is mostly because of its high flexibility in threshold adjustment. Other popular technologies are graphene nanoribbon FET [34,47,60,75,76] and memristor [22,23,26,63,[77][78][79][80]. A fusion of two technologies has sometimes been exploited.…”

“…This popularity is mostly because of its high flexibility in threshold adjustment. Other popular technologies are graphene nanoribbon FET [34, 47, 60, 75, 76] and memristor [22, 23, 26, 63, 77–80]. A fusion of two technologies has sometimes been exploited. Balanced versus Unbalanced (Figure 3b): There are two ways to define ternary digits (trits) in base 3: i ) Balanced (or signed) with the number set {−1, 0, +1} 3 , and ii ) Unbalanced (or unsigned) with the number set {0, 1, 2} 3 .…”

“…We have found 125 related papers [11–135], 20% of which have been published in IEEE journals. To be more specific, there are 15 IEEE Transactions [11–25], five IEEE Access [26–30], and two JSSC papers [31, 32].…”

A gate‐tunable memristor emulator for motion detection

“…It is difficult to achieve multi-value effects with traditional dual-port memristors, and it requires additional circuit consumption when designing large-scale memristor arrays. 19,20 In Zhang et al, 21 it was demonstrated that quantized current was a result of formation of tree-shaped conductive filaments inside the memristor with the SET/RSET process being controlled by the application of gate voltage. The electrical symbol of the gate-tunable memristor is shown in Figure 1A, and its approach to achieving multiple resistance states by applying different gate voltage to change its hysteresis loop is shown in Figure 1B.…”

“…With memristor arrays, more individual memristor resistance values enable higher quantization accuracy to be achieved. It is difficult to achieve multi‐value effects with traditional dual‐port memristors, and it requires additional circuit consumption when designing large‐scale memristor arrays 19,20 . In Zhang et al, 21 it was demonstrated that quantized current was a result of formation of tree‐shaped conductive filaments inside the memristor with the SET/RSET process being controlled by the application of gate voltage.…”