A theoretical and experimental study of the noise behavior of subharmonically injection locked local oscillators

Zhang, X.; Zhou, Xia; Daryoush, A.S.

doi:10.1109/22.137395

Cited by 128 publications

(56 citation statements)

References 18 publications

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“…Assuming that ILO ( ), REF ( ), and VCO ( ) are phase noise power functions of an injection-locked VCO, a reference signal, and a free-running VCO, respectively, the phase noise of an ILO, ILO ( ), simply can be expressed as high-pass transfer functions, respectively [8]. Supposed that HPF ( ) and LPF ( ) have the first-order transfer functions and they have the same cutoff frequency of , the simple equation of (4) would be achieved [5,9,10].…”

Section: Injection Locking In Frequency Synthesizersmentioning

confidence: 99%

“…From the calculated result of = /2 = 40 MHz, (4) is well matched to the measurement results except the offset-frequency region up to about 30 kHz. It is because that flicker noise model as expressed in [5] is not included for simplicity and certain spurs occurred at the offset frequency of about 10 KHz were measured.…”

Section: Main Pll (Mpll)mentioning

confidence: 99%

“…In designing subharmonically injection-locked oscillators (ILOs), times frequency-multiplied signals as to the reference frequency can be achieved. The lock range is decided by the power of th superharmonics of the reference signal as follows [1,5]:…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

Lee

Ito

Amakawa

et al. 2013

International Journal of Microwave Science and Technology

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An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm 2 ) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates highfrequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).

show abstract

Section: Injection Locking In Frequency Synthesizersmentioning

confidence: 99%

Section: Main Pll (Mpll)mentioning

confidence: 99%

See 1 more Smart Citation

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

Lee

Ito

Amakawa

et al. 2013

International Journal of Microwave Science and Technology

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“…where Q represents the open-loop quality factor of an oscillator (calculated by using the open-loop transfer function of the oscillator), ω out is the output frequency of the oscillator under injection-locked condition, P injM is M th harmonic power of the injection pulse signal and P osc is the free-running output power of the oscillator [6]. Fig.…”

Section: Proposed Ilffmmentioning

confidence: 99%

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique

Lee

Ito

Tanoi

et al. 2012

IEICE Electron. Express

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An injection-locked fractional frequency multiplier (IL-FFM) based on a ring VCO is proposed. The ILFFM can output signals whose output-frequency step equal quarter of an input reference frequency (1/4 × f ref ), with low-phase-noise characteristics due to injection locking. To realize this fractional frequency multiplication, an injection pulse selection circuit is demonstrated, which can select the appropriate injection pulse trains as to the VCO output phases.

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“…This synchronization regime presents common features with harmonic (M = 1) [6,7,12,13], and with sub-harmonic synchronization (N = 1) [14,15]. Therefore, for a given value of the reference signal power, the synchronization range depends on the harmonic content and the quality factor of the circuit [16].…”

Section: Designmentioning

confidence: 99%

Optimization of the Synchronization Bandwidth of Rationally Synchronized Oscillators Based on Bifurcation Control

Fernández¹,

Hoeye²,

Vázquez³

et al. 2011

PIER

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Abstract-In this work, a nonlinear technique for the optimization of the synchronization bandwidth of Rationally Synchronized Oscillators (RSO) is presented. The circuit is forced to operate near a Hopf bifurcation point which is created around the frequency of the input reference signal. Under this operating regime, the reference signal is strongly amplified and the synchronization bandwidth of the circuit is considerably improved. A 5-3 GHz rationally synchronized oscillator has been optimized using the proposed method. The manufactured RSO provides a 5 MHz synchronization bandwidth with a reference signal power of −22 dBm, in good agreement with simulation results.

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A theoretical and experimental study of the noise behavior of subharmonically injection locked local oscillators

Cited by 128 publications

References 18 publications

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique

Optimization of the Synchronization Bandwidth of Rationally Synchronized Oscillators Based on Bifurcation Control

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