A Time-to-Digital Converter Based on a Digitally Controlled Oscillator

Cadeddu, S.; Aloisio, A.; Ameli, F.; Bocci, V.; Casu, L.; Giordano, R.; Izzo, V.; Lai, A.; Loi, A.; Mastroianni, S.

doi:10.1109/tns.2017.2726822

Cited by 5 publications

(5 citation statements)

References 21 publications

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“…Solutions [11,15,16] and [17] are characterized by smaller power consumption and LSB but they have been developed in a more advanced technological node and, as explained in section 1, the complexity and/or the limited maximum measurable time interval make them more difficult to be integrated in large pixel detector chips. The non-linearities of the presented -18 -2021 JINST 16 P11023 1 and the ones reported in [24][25][26][27][28][29][30][31][32][33][34][35][36]. The size of the dots on the plot is proportional to the power consumption of the analyzed TDCs (logarithmic scale).…”

Section: State-of-the-art Comparisonmentioning

confidence: 66%

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A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

Martinelli¹,

Valerio²,

Cardarelli³

et al. 2021

J. Inst.

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A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.

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Section: State-of-the-art Comparisonmentioning

confidence: 66%

“…Figure20. Area and LSB of the presented TDC compared to the works of table 1 and the ones reported in[24][25][26][27][28][29][30][31][32][33][34][35][36]. The size of the dots on the plot is proportional to the power consumption of the analyzed TDCs (logarithmic scale).…”

mentioning

confidence: 92%

A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

Martinelli¹,

Valerio²,

Cardarelli³

et al. 2021

J. Inst.

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“…The main purpose of the nSYNC is to time align digital data arriving from front-end electronics, corresponding to hits in the muon chambers, tag them with the bunch crossing identification number and finally format and send the information out through 14 LVDS links. In each of the 48 input channels the signal arrival time is measured by a TDC, which uses a fully digital DCO and is equipped with a dithering correction system [3]. The TDC can work with several time resolutions, i.e.…”

Section: Nsync Architecture and Radiation Hardnessmentioning

confidence: 99%

Radiation hardness test of the nSYNC ASIC with 60 MeV proton beam

Brundu¹,

Cadeddu²,

Cardini³

et al. 2019

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)

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“…To address the challenges encountered in deep submicrometer CMOS technology, researchers and manufacturers adopt a digital-intensive approach to effectively control the frequency of oscillation. Consequently, the Voltage-Controlled Oscillator (VCO) is replaced with the Digital Controlled Oscillator (DCO) [7][8][9][10][11]. The oscillator circuit that employs a digital-intensive approach to regulate the frequency range is commonly referred to as a digitally controlled oscillator (DCO).…”

Section: Introductionmentioning

confidence: 99%

“…In certain applications, electronic systems require a xed frequency range instead of a variable range of frequencies. For these speci c scenarios, Digital Controlled Oscillator (DCO) circuits offer the advantage of generating a xed range of frequencies with reduced power consumption [10,12].…”

Section: Introductionmentioning

confidence: 99%

A Low Power Hybrid DCO using Three transistor (3-T) XNOR gate, CMOS and Pseudo-NMOS inverter

bagri,

kumar,

kumar

2023

Preprint

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This research article presents a comprehensive investigation of three-bit hybrid-digitally controlled ring oscillator (HDCRO) implemented with TMSC 90nm CMOS technology.The hybrid circuit HDCRO comprises of three distinct delay stages, namely XNOR-based inverter, a CMOS inverter, and a Pseudo-NMOS inverter, all of which have been designed utilizing an inversion MOS varactor (IMOS). Furthermore, the investigation explores the output frequency variation in the load element of the HDCRO by adjusting the capacitance of the digitally controlled MOS varactors. This frequency variation occurs as a result of changing the digital control bits of the MOS varactors at a supply voltage of 0.7 V. The proposed HDCRO demonstrates an oscillation frequency range of 2.558 GHz to 2.649 GHz, with power consumption varying from 3.638 mW to 1.046 mW, and phase noise from -68.070 dB@1 MHz to -67.654 dB@1 MHz relative to the central oscillation frequency. Moreover, by applying a supply voltage variation between 0.5 V and 1 V, a wider frequency tuning range of 1.238 GHz to 4.438 GHz is achieved. This extended tuning range exhibits power consumption variation from 2.785 µW to 54.66 mW, and phase noise from -68.812 dB@1 MHz to -65.445 dB@1 MHz relative to the central oscillation frequency. In summary, this study presents a novel HDCRO architecture that demonstrates excellent performance in terms of frequency range, power consumption and phase noise. The proposed design offers advantages of high speed, low-power and good frequency range; thus has a promising prospect of application in high-performance integrated circuits.

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A Time-to-Digital Converter Based on a Digitally Controlled Oscillator

Cited by 5 publications

References 21 publications

A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

Radiation hardness test of the nSYNC ASIC with 60 MeV proton beam

A Low Power Hybrid DCO using Three transistor (3-T) XNOR gate, CMOS and Pseudo-NMOS inverter

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