A timing driven N-way chip and multi-chip partitioner

Abstract

With the growing complexity of integrated circuits and the advent of new technologies and new generations of packaging technologies, an essential physical design tool is a flexible physical panitioner. We therefore present a timing driven n-way chip and multi-chip partitioner which we call Tomus. The panitioner enables an automatic layout package to I ) divide and conquer the physical design process of Field Programmable Gate Array (FPGA) circuits or mixed macro/standard cell circuits and 2 ) physically partition a circuit onto n chips for a multichip package. Using a two-phased natural and adaptive clustering method, the annealing-based N-way partitioner executes four to 22 times faster with improved partitioning results. The placement results for industrial FPGAs were improved by 9Wo over the only available industrial placement tool. Our partitioner outpevormed an industrial FPGA partitioner by 95% in MCM partitioning.

From real-time emulation to ASIC integration for image processing applications

“…This implies that a partitioning of the DFP graph was performed. This problem has not been addressed in Much research is being done in the domain of constraint-driven partitioning, e.g., [16] (area and speed optimization), [17] (wire length and speed optimization), [18] (area and pincount optimization). Partitioning a DFP graph should benefit from the highly hierarchical nature of such graphs.…”

Multi-way partitioning for minimum delay for look-up table based FPGAs

“…Several approaches have been proposed on partitioning for FPGAs [1,2,3]. Kuznar [1,2] associates a $cost to each FPGA device and uses a bi-partitioner recursively to arrive at a multi-way partition that minimizes the $cost and interconnection costs of the partition.…”

“…Kuznar [1,2] associates a $cost to each FPGA device and uses a bi-partitioner recursively to arrive at a multi-way partition that minimizes the $cost and interconnection costs of the partition. Sechen [3] first identifies clusters, and then uses a simulated annealing based placement of clusters on to an MCM to minimize wirelength and timing penalty.…”

Performance-driven simultaneous place and route for row-based FPGAs

“…The bipartitioning technique is either modified [14] or used iteratively [15] to achieve k-way partitions. Some methods also employ simulated annealing [3]for partition optimization [18].…”