A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

Landman, P.; Brouse, K.; Gupta, Vikas; Wu, Song; Payne, Robert; Erdogan, U.; Gu, R.; Yee, Ah-Lyan; Parthasarathy, B.; Ramaswamy, S.; Bhakta, B.; Mohammed, Wahed; Powers, John; Xie, Youbai; Wu, Longwen; Dyson, L.; Heragu, K.; Lee, Wai

doi:10.1109/isscc.2005.1493871

Cited by 11 publications

(8 citation statements)

References 3 publications

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“…The PLL is designed for a 6.25 Gb/s to 12.5 Gb/s backplane data transmission in communication systems [2] [3]. To enable operation over 6.25 GHz, a high-speed version of 0.13 μm CMOS process is chosen which operates at minimum 1 V supply voltage.…”

Section: Introductionmentioning

confidence: 99%

An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS

Lee

2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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A 6.25 GHz PLL with an integrated LC-tank VCO designed and fabricated in 0.13 μm CMOS technology is described. For a deep submicron CMOS technology, leakage currents and limited voltage headroom degrade PLL performance. This paper introduces a new charge pump design with rail-to-rail operation and leakage cancellation techniques to overcome these constraints. Operated at 1 V supply voltage with an input reference clock frequency of 62.5 MHz, the PLL has 0.5 ps rms jitter at output frequency of 6.25 GHz.

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Section: Introductionmentioning

confidence: 99%

An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS

Lee

2006

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings

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“…The feed-forward equalizer (FFE) cancels the precursor ISI while a decision feedback equalizer (DFE) [9] uses a linear combination of past decisions to cancel the post-cursor ISI. In the analog domain, a FFE is realized by summing the outputs of a fixed-gain DC path and a variable-gain AC path, resulting in a continuoustime finite-impulse-response (FIR) filter [10] or an infinite-impulse-response (IIR) filter [11].…”

Section: Equalizationmentioning

confidence: 99%

“…around 12Gb/s). Using an FFE and DFE together addresses these concerns [10,11,[15][16][17]. In [10], a backplane link transceiver architecture, implemented in 0.13µm CMOS technology, incorporates a 4-tap FFE (FIR) that in conjunction with a DFE enables 6.25/12.5Gb/s data transmission.…”

Section: Equalizationmentioning

confidence: 99%

“…Using an FFE and DFE together addresses these concerns [10,11,[15][16][17]. In [10], a backplane link transceiver architecture, implemented in 0.13µm CMOS technology, incorporates a 4-tap FFE (FIR) that in conjunction with a DFE enables 6.25/12.5Gb/s data transmission. In [11] a 2-tap preemphasis network in the transmitter, along with a 1-tap FFE (IIR) and 3-tap DFE structure in the receiver is used in a 5Gb/s NRZ transceiver to achieve a BER of less than 10 -15 in the presence of crosstalk.…”

Section: Equalizationmentioning

confidence: 99%

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Recent advances in high-speed serial I/O trends, standards and techniques

Noel

Zarkeshvari

Kwaśniewski

Canadian Conference on Electrical and Computer Engineering, 2005.

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“…TX data can be a (2 32 -1) bit PRBS or an externally loaded 140-bit pattern which subsequently passes through a bypass-able 8B/10B encoder. Two TX designs were implemented: the low-power TX with 2-tap equalized voltagemode (V-mode) driver [1], and the high-performance TX with 2-way interleaved 2 to 6-tap programmable MAC (multiplyaccumulate) based FIR TX equalizers and a 6-bit DAC currentmode (I-mode) driver [2]. Both support swings up to 600mV.…”

mentioning

confidence: 99%

Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

Yeung

Canagasaby

Tripathi

et al.

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/O links in a 1.2V 90nm CMOS test chip implementing equalized voltage-mode and current-mode drivers, TX and RX equalizers, self-biased ring oscillator and LC PLLs, and different RX clocking schemes are compared. The novel combination of voltage-mode driver (equalized or unequalized) and RX equalizer delivers the lowest power (12.1mW/Gbps at 7.2Gbps), offering a low-power option for short-distance links. (Keywords: low power, I/O link, equalizer, voltage-mode driver) IntroductionThe 3 key metrics in Gigabit I/O designs are performance (data rate), power, and channel length. Different tradeoffs are made depending on system requirements. In server interconnections, the major challenge is to overcome the harsh channel conditions. Sophisticated equalizers are implemented to increase the data rate and distance at the expense of increased power. On the other hand, I/Os for desktop and mobile systems need cheaper cooling solutions, making power optimization the most important design metric. This is especially true for mobile I/Os, where the power is further limited by battery capacities.Transceiver System A high-speed transceiver test chip containing I/O links for server, desktop, and mobile applications was implemented in a 1.2V, 90nm digital CMOS process. The chip contains 2 I/O ports on the 2 sides of a 5mm x 5mm die, with shared circuitry and digital blocks situated in the middle, as shown in Figure 1. Two packages, a land-grid array and a ball-grid array, allow the packaged chip to be placed in a socket or soldered directly on a test board. Figure 2 shows the architecture of each port, which contains 6 differential data lanes and 1 differential clock lane. A halfrate TxClk is generated by a TxPLL, which can be an LC-PLL or a self-biased ring oscillator PLL (SBRO-PLL) shared between the ports, and distributed to all I/Os using CMOS buffers. TX data can be a (2 32 -1) bit PRBS or an externally loaded 140-bit pattern which subsequently passes through a bypass-able 8B/10B encoder. Two TX designs were implemented: the low-power TX with 2-tap equalized voltagemode (V-mode) driver [1], and the high-performance TX with 2-way interleaved 2 to 6-tap programmable MAC (multiplyaccumulate) based FIR TX equalizers and a 6-bit DAC currentmode (I-mode) driver [2]. Both support swings up to 600mV.At RX, a DLL generates 8 global clock phases at 45 o spacings from a half-rate forwarded clock or a SBRO-PLL (labeled RxPLL) locked to a reference (local) clock. The clock phases are distributed to all I/Os where they are phase multiplexed and interpolated to generate the skewed RxClks.

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A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications

Cited by 11 publications

References 3 publications

An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS

An 1 V 6.25 GHz PLL with 0.5 ps rms Jitter in 0.13 /spl mu/m CMOS

Recent advances in high-speed serial I/O trends, standards and techniques

Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

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